drm/xe/mtl: Fix PAT table coherency settings

Re-sync our MTL PAT table with the bspec.  1-way coherency should only
be set on table entry 3.  We do not want an incorrect setting here to
accidentally paper over other bugs elsewhere in the driver.

Bspec: 45101
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
Link: https://lore.kernel.org/r/20230324210415.2434992-6-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c
index d2935ef0e274ecaea07dd41bbe5d707a328ad03c..e83f7895b85377b43c73a66f4d9bfdc678be97c5 100644 (file)
--- a/drivers/gpu/drm/xe/xe_pat.c
+++ b/drivers/gpu/drm/xe/xe_pat.c
@@ -54,8 +54,8 @@ const u32 pvc_pat_table[] = {
 
 const u32 mtl_pat_table[] = {
        [0] = MTL_PAT_0_WB,
-       [1] = MTL_PAT_1_WT | MTL_2_COH_1W,
-       [2] = MTL_PAT_3_UC | MTL_2_COH_1W,
+       [1] = MTL_PAT_1_WT,
+       [2] = MTL_PAT_3_UC,
        [3] = MTL_PAT_0_WB | MTL_2_COH_1W,
        [4] = MTL_PAT_0_WB | MTL_3_COH_2W,
 };