arm64: dts: mediatek: mt8192: Fix systimer 13 MHz clock description

The systimer block derives its 13 MHz clock by dividing the main 26 MHz
oscillator clock by 2 internally, not through the TOPCKGEN clock
controller.

On the MT8192 this divider is fixed to /2 and is not configurable.

Making the systimer block take the 26 MHz clock directly requires
changing the implementations. As an ABI compatible fix, change the
input clock of the systimer block a fixed factor divide-by-2 clock
that takes the 26 MHz oscillator as its input.

Fixes: 48489980e27e ("arm64: dts: Add Mediatek SoC MT8192 and evaluation board dts and Makefile")
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221201084229.3464449-3-wenst@chromium.org
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 424fc89cc6f7cb8930bff15acfb9f729e31ffe11..0d43a32734a377729c808552f3b53e0baf168e01 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -29,6 +29,15 @@
                rdma4 = &rdma4;
        };
 
+       clk13m: fixed-factor-clock-13m {
+               compatible = "fixed-factor-clock";
+               #clock-cells = <0>;
+               clocks = <&clk26m>;
+               clock-div = <2>;
+               clock-mult = <1>;
+               clock-output-names = "clk13m";
+       };
+
        clk26m: oscillator0 {
                compatible = "fixed-clock";
                #clock-cells = <0>;
@@ -534,8 +543,7 @@
                                     "mediatek,mt6765-timer";
                        reg = <0 0x10017000 0 0x1000>;
                        interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>;
-                       clocks = <&topckgen CLK_TOP_CSW_F26M_D2>;
-                       clock-names = "clk13m";
+                       clocks = <&clk13m>;
                };
 
                pwrap: pwrap@10026000 {