habanalabs: update to latest hl_boot_if.h spec from F/W
authorOded Gabbay <ogabbay@kernel.org>
Tue, 26 Jan 2021 20:59:35 +0000 (22:59 +0200)
committerOded Gabbay <ogabbay@kernel.org>
Wed, 27 Jan 2021 19:03:51 +0000 (21:03 +0200)
It adds the definition for indication that the F/W handles HBM ECC
events.

Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
drivers/misc/habanalabs/include/common/hl_boot_if.h

index e29c77bdea07720d1a2ea3ed6bbabb1abe74a636..57785478a4ef840fd14ebe95e9252d0c8d58881d 100644 (file)
@@ -69,8 +69,9 @@
  *                                     image has failed to match expected
  *                                     checksum. Trying to program image again
  *                                     might solve this.
+ *
  * CPU_BOOT_ERR0_PLL_FAIL              PLL settings failed, meaning that one
- *                                     of the PLLs remained in REF_CLK
+ *                                     of the PLLs remains in REF_CLK
  *
  * CPU_BOOT_ERR0_ENABLED               Error registers enabled.
  *                                     This is a main indication that the
  *                                     FW initialized Clock Gating.
  *                                     Initialized in: preboot
  *
+ * CPU_BOOT_DEV_STS0_HBM_ECC_EN                HBM ECC handling Enabled.
+ *                                     FW handles HBM ECC indications.
+ *                                     Initialized in: linux
+ *
  * CPU_BOOT_DEV_STS0_ENABLED           Device status register enabled.
  *                                     This is a main indication that the
  *                                     running FW populates the device status
 #define CPU_BOOT_DEV_STS0_PLL_INFO_EN                  (1 << 11)
 #define CPU_BOOT_DEV_STS0_SP_SRAM_EN                   (1 << 12)
 #define CPU_BOOT_DEV_STS0_CLK_GATE_EN                  (1 << 13)
+#define CPU_BOOT_DEV_STS0_HBM_ECC_EN                   (1 << 14)
 #define CPU_BOOT_DEV_STS0_ENABLED                      (1 << 31)
 
 enum cpu_boot_status {