arm64: dts: freescale: ls1028a: Fix embedded PCI interrupt mapping

PCI devices should use PCI interrupt binding for their interrupts assuming
they function as standard PCI interrupts. The embedded PCI devices in the
LS1028a are mapping the interrupts directly to the host interrupt
controller. While that works here, it is unusual.

Based on the reference manual, there is not any INTC or INTD to map, so
only INTA and INTB are mapped.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index ae534c23b970a2f58558bee9e1ec0940579adf02..8f81799248510d1ea9caa79f0c53cacb59dd33ff 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -1099,6 +1099,10 @@
                                  0xc2000000 0x1 0xf8230000  0x1 0xf8230000  0x0 0x020000
                                  /* BAR4 (PF5) - non-prefetchable memory */
                                  0x82000000 0x1 0xfc000000  0x1 0xfc000000  0x0 0x400000>;
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 7>;
+                       interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0000 0 0 2 &gic 0 0 GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 
                        enetc_port0: ethernet@0,0 {
                                compatible = "fsl,enetc";
@@ -1143,7 +1147,7 @@
                        mscc_felix: ethernet-switch@0,5 {
                                reg = <0x000500 0 0 0 0>;
                                /* IEP INT_B */
-                               interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupts = <2>;
                                status = "disabled";
 
                                mscc_felix_ports: ports {
@@ -1216,7 +1220,7 @@
                        rcec@1f,0 {
                                reg = <0x00f800 0 0 0 0>;
                                /* IEP INT_A */
-                               interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupts = <1>;
                        };
                };