drm/i915/cdclk: Rewrite cdclk->voltage_level selection to use tables

The cdclk->voltage_level if ladders are hard to read, especially as
they're written the other way around compared to how bspec lists
the limits. Let's rewrite them to use simple arrays that gives us
the max cdclk for each voltage level.

v2: Bump the jsl/ehl max cdclk in the table to 652.8 MHz to
    accommodate JSL machines in CI that boot with high cdclk

Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231211221759.29725-1-ville.syrjala@linux.intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index a12cf085dbdb45c6fce1d37278633cbf99caf935..a1d87db2665b7dd3ecb8aef5dbbd1fed62b9867c 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1446,50 +1446,77 @@ static u8 bxt_calc_voltage_level(int cdclk)
        return DIV_ROUND_UP(cdclk, 25000);
 }
 
+static u8 calc_voltage_level(int cdclk, int num_voltage_levels,
+                            const int voltage_level_max_cdclk[])
+{
+       int voltage_level;
+
+       for (voltage_level = 0; voltage_level < num_voltage_levels; voltage_level++) {
+               if (cdclk <= voltage_level_max_cdclk[voltage_level])
+                       return voltage_level;
+       }
+
+       MISSING_CASE(cdclk);
+       return num_voltage_levels - 1;
+}
+
 static u8 icl_calc_voltage_level(int cdclk)
 {
-       if (cdclk > 556800)
-               return 2;
-       else if (cdclk > 312000)
-               return 1;
-       else
-               return 0;
+       static const int icl_voltage_level_max_cdclk[] = {
+               [0] = 312000,
+               [1] = 556800,
+               [2] = 652800,
+       };
+
+       return calc_voltage_level(cdclk,
+                                 ARRAY_SIZE(icl_voltage_level_max_cdclk),
+                                 icl_voltage_level_max_cdclk);
 }
 
 static u8 ehl_calc_voltage_level(int cdclk)
 {
-       if (cdclk > 326400)
-               return 3;
-       else if (cdclk > 312000)
-               return 2;
-       else if (cdclk > 180000)
-               return 1;
-       else
-               return 0;
+       static const int ehl_voltage_level_max_cdclk[] = {
+               [0] = 180000,
+               [1] = 312000,
+               [2] = 326400,
+               /*
+                * Bspec lists the limit as 556.8 MHz, but some JSL
+                * development boards (at least) boot with 652.8 MHz
+                */
+               [3] = 652800,
+       };
+
+       return calc_voltage_level(cdclk,
+                                 ARRAY_SIZE(ehl_voltage_level_max_cdclk),
+                                 ehl_voltage_level_max_cdclk);
 }
 
 static u8 tgl_calc_voltage_level(int cdclk)
 {
-       if (cdclk > 556800)
-               return 3;
-       else if (cdclk > 326400)
-               return 2;
-       else if (cdclk > 312000)
-               return 1;
-       else
-               return 0;
+       static const int tgl_voltage_level_max_cdclk[] = {
+               [0] = 312000,
+               [1] = 326400,
+               [2] = 556800,
+               [3] = 652800,
+       };
+
+       return calc_voltage_level(cdclk,
+                                 ARRAY_SIZE(tgl_voltage_level_max_cdclk),
+                                 tgl_voltage_level_max_cdclk);
 }
 
 static u8 rplu_calc_voltage_level(int cdclk)
 {
-       if (cdclk > 556800)
-               return 3;
-       else if (cdclk > 480000)
-               return 2;
-       else if (cdclk > 312000)
-               return 1;
-       else
-               return 0;
+       static const int rplu_voltage_level_max_cdclk[] = {
+               [0] = 312000,
+               [1] = 480000,
+               [2] = 556800,
+               [3] = 652800,
+       };
+
+       return calc_voltage_level(cdclk,
+                                 ARRAY_SIZE(rplu_voltage_level_max_cdclk),
+                                 rplu_voltage_level_max_cdclk);
 }
 
 static void icl_readout_refclk(struct drm_i915_private *dev_priv,