drm/i915: Nuke PCH_MCC
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Thu, 30 Jun 2022 15:05:59 +0000 (18:05 +0300)
committerVille Syrjälä <ville.syrjala@linux.intel.com>
Wed, 6 Jul 2022 17:33:32 +0000 (20:33 +0300)
MCC is derived from TGP, and we have no real need to
differentiate between the two. Thus remove PCH_MCC and
just declare it to be PCH_TGP compatible.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220630150600.24611-3-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
drivers/gpu/drm/i915/display/intel_ddi.c
drivers/gpu/drm/i915/display/intel_hdmi.c
drivers/gpu/drm/i915/intel_pch.c
drivers/gpu/drm/i915/intel_pch.h

index 5d448e0563be470dcefdb1735c8e8405a5d81d76..f76eb6e345ec92eff7b7360d9c51a19a12d43e71 100644 (file)
@@ -4179,7 +4179,7 @@ static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv,
        if (port == PORT_D)
                return HPD_PORT_A;
 
-       if (HAS_PCH_MCC(dev_priv))
+       if (HAS_PCH_TGP(dev_priv))
                return icl_hpd_pin(dev_priv, port);
 
        return HPD_PORT_A + port - PORT_A;
index a4a6f8bd2841e64a6fe56a3ff0e3d94cf3cdce5e..cb6898cbe1c8ff7efdb9b2d08fd598b2675621c9 100644 (file)
@@ -2851,7 +2851,7 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
                ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
        else if (DISPLAY_VER(dev_priv) == 9 && HAS_PCH_TGP(dev_priv))
                ddc_pin = gen9bc_tgp_port_to_ddc_pin(dev_priv, port);
-       else if (HAS_PCH_MCC(dev_priv))
+       else if (IS_JSL_EHL(dev_priv) && HAS_PCH_TGP(dev_priv))
                ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
        else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
                ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
index 94446cac6605262aa28e5cf4e69729399e1428cc..b45c504c6f0334512f28265225e9b40536b7794c 100644 (file)
@@ -116,7 +116,8 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
        case INTEL_PCH_MCC_DEVICE_ID_TYPE:
                drm_dbg_kms(&dev_priv->drm, "Found Mule Creek Canyon PCH\n");
                drm_WARN_ON(&dev_priv->drm, !IS_JSL_EHL(dev_priv));
-               return PCH_MCC;
+               /* MCC is TGP compatible */
+               return PCH_TGP;
        case INTEL_PCH_TGP_DEVICE_ID_TYPE:
        case INTEL_PCH_TGP2_DEVICE_ID_TYPE:
                drm_dbg_kms(&dev_priv->drm, "Found Tiger Lake LP PCH\n");
index b7a8cf409d48345d205e90d88cd118b782feb09a..07f6f5517968d362a532cb06842388238e33eddc 100644 (file)
@@ -24,8 +24,7 @@ enum intel_pch {
        PCH_CNP,        /* Cannon/Comet Lake PCH */
        PCH_ICP,        /* Ice Lake PCH */
        PCH_JSP,        /* Jasper Lake PCH */
-       PCH_MCC,        /* Mule Creek Canyon PCH */
-       PCH_TGP,        /* Tiger Lake PCH */
+       PCH_TGP,        /* Tiger Lake/Mule Creek Canyon PCH */
        PCH_ADP,        /* Alder Lake PCH */
 
        /* Fake PCHs, functionality handled on the same PCI dev */
@@ -69,7 +68,6 @@ enum intel_pch {
 #define HAS_PCH_ADP(dev_priv)                  (INTEL_PCH_TYPE(dev_priv) == PCH_ADP)
 #define HAS_PCH_DG1(dev_priv)                  (INTEL_PCH_TYPE(dev_priv) == PCH_DG1)
 #define HAS_PCH_JSP(dev_priv)                  (INTEL_PCH_TYPE(dev_priv) == PCH_JSP)
-#define HAS_PCH_MCC(dev_priv)                  (INTEL_PCH_TYPE(dev_priv) == PCH_MCC)
 #define HAS_PCH_TGP(dev_priv)                  (INTEL_PCH_TYPE(dev_priv) == PCH_TGP)
 #define HAS_PCH_ICP(dev_priv)                  (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
 #define HAS_PCH_CNP(dev_priv)                  (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)