<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&versaclock6_bb 4>, <&audio_clk_b>,
<&audio_clk_c>,
- <&cpg CPG_CORE CPG_AUDIO_CLK_I>;
+ <&cpg CPG_MOD 922>;
status = "okay";
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&cs2000>,
<&audio_clk_c>,
- <&cpg CPG_CORE CPG_AUDIO_CLK_I>;
+ <&cpg CPG_MOD 922>;
rsnd_port: port {
rsnd_endpoint: endpoint {
#include <dt-bindings/clock/r8a774a1-cpg-mssr.h>
#include <dt-bindings/power/r8a774a1-sysc.h>
-#define CPG_AUDIO_CLK_I R8A774A1_CLK_S0D4
-
/ {
compatible = "renesas,r8a774a1";
#address-cells = <2>;
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&audio_clk_b>,
<&audio_clk_c>,
- <&cpg CPG_CORE R8A774A1_CLK_S0D4>;
+ <&cpg CPG_MOD 922>;
clock-names = "ssi-all",
"ssi.9", "ssi.8", "ssi.7", "ssi.6",
"ssi.5", "ssi.4", "ssi.3", "ssi.2",
#include <dt-bindings/clock/r8a774b1-cpg-mssr.h>
#include <dt-bindings/power/r8a774b1-sysc.h>
-#define CPG_AUDIO_CLK_I R8A774B1_CLK_S0D4
-
/ {
compatible = "renesas,r8a774b1";
#address-cells = <2>;
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&audio_clk_b>,
<&audio_clk_c>,
- <&cpg CPG_CORE R8A774B1_CLK_S0D4>;
+ <&cpg CPG_MOD 922>;
clock-names = "ssi-all",
"ssi.9", "ssi.8", "ssi.7", "ssi.6",
"ssi.5", "ssi.4", "ssi.3", "ssi.2",
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&audio_clk_b>,
<&audio_clk_c>,
- <&cpg CPG_CORE R8A774C0_CLK_ZA2>;
+ <&cpg CPG_MOD 922>;
clock-names = "ssi-all",
"ssi.9", "ssi.8", "ssi.7", "ssi.6",
"ssi.5", "ssi.4", "ssi.3", "ssi.2",
#include <dt-bindings/clock/r8a774e1-cpg-mssr.h>
#include <dt-bindings/power/r8a774e1-sysc.h>
-#define CPG_AUDIO_CLK_I R8A774E1_CLK_S0D4
-
/ {
compatible = "renesas,r8a774e1";
#address-cells = <2>;
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&audio_clk_b>,
<&audio_clk_c>,
- <&cpg CPG_CORE R8A774E1_CLK_S0D4>;
+ <&cpg CPG_MOD 922>;
clock-names = "ssi-all",
"ssi.9", "ssi.8", "ssi.7", "ssi.6",
"ssi.5", "ssi.4", "ssi.3", "ssi.2",
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a7795-sysc.h>
-#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4
-
#define SOC_HAS_HDMI1
#define SOC_HAS_SATA
#define SOC_HAS_USB2_CH2
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&audio_clk_b>,
<&audio_clk_c>,
- <&cpg CPG_CORE R8A7795_CLK_S0D4>;
+ <&cpg CPG_MOD 922>;
clock-names = "ssi-all",
"ssi.9", "ssi.8", "ssi.7", "ssi.6",
"ssi.5", "ssi.4", "ssi.3", "ssi.2",
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a7796-sysc.h>
-#define CPG_AUDIO_CLK_I R8A7796_CLK_S0D4
-
/ {
compatible = "renesas,r8a7796";
#address-cells = <2>;
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&audio_clk_b>,
<&audio_clk_c>,
- <&cpg CPG_CORE R8A7796_CLK_S0D4>;
+ <&cpg CPG_MOD 922>;
clock-names = "ssi-all",
"ssi.9", "ssi.8", "ssi.7", "ssi.6",
"ssi.5", "ssi.4", "ssi.3", "ssi.2",
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a77961-sysc.h>
-#define CPG_AUDIO_CLK_I R8A77961_CLK_S0D4
-
/ {
compatible = "renesas,r8a77961";
#address-cells = <2>;
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&audio_clk_b>,
<&audio_clk_c>,
- <&cpg CPG_CORE R8A77961_CLK_S0D4>;
+ <&cpg CPG_MOD 922>;
clock-names = "ssi-all",
"ssi.9", "ssi.8", "ssi.7", "ssi.6",
"ssi.5", "ssi.4", "ssi.3", "ssi.2",
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a77965-sysc.h>
-#define CPG_AUDIO_CLK_I R8A77965_CLK_S0D4
-
#define SOC_HAS_SATA
/ {
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&audio_clk_b>,
<&audio_clk_c>,
- <&cpg CPG_CORE R8A77965_CLK_S0D4>;
+ <&cpg CPG_MOD 922>;
clock-names = "ssi-all",
"ssi.9", "ssi.8", "ssi.7", "ssi.6",
"ssi.5", "ssi.4", "ssi.3", "ssi.2",
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&audio_clk_b>,
<&audio_clk_c>,
- <&cpg CPG_CORE R8A77990_CLK_ZA2>;
+ <&cpg CPG_MOD 922>;
clock-names = "ssi-all",
"ssi.9", "ssi.8", "ssi.7", "ssi.6",
"ssi.5", "ssi.4", "ssi.3", "ssi.2",
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&audio_clk_b>,
- <&cpg CPG_CORE R8A77995_CLK_ZA2>;
+ <&cpg CPG_MOD 922>;
clock-names = "ssi-all",
"ssi.4", "ssi.3",
"src.6", "src.5",
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&cs2000>,
<&audio_clk_c>,
- <&cpg CPG_CORE CPG_AUDIO_CLK_I>;
+ <&cpg CPG_MOD 922>;
ports {
#address-cells = <1>;
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&cs2000>,
<&audio_clk_c>,
- <&cpg CPG_CORE CPG_AUDIO_CLK_I>;
+ <&cpg CPG_MOD 922>;
};
&rpc {