arm64: dts: ti: k3-j721e-common-proc-board: Use external clock for SERDES

Use external clock for all the SERDES used by PCIe controller. This will
make the same clock used by the local SERDES as well as the clock
provided to the PCIe connector.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210603143427.28735-4-kishon@ti.com

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index 498e31052a2b40d8a8fffe7d2c82b86dfa65383c..8e7e013f9fffea00e9ecc708e6cc15a0c6c8a89b 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -9,6 +9,7 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/phy/phy-cadence.h>
 
 / {
        chosen {
@@ -639,7 +640,40 @@
        clock-frequency = <100000000>;
 };
 
+&wiz0_pll1_refclk {
+       assigned-clocks = <&wiz0_pll1_refclk>;
+       assigned-clock-parents = <&cmn_refclk1>;
+};
+
+&wiz0_refclk_dig {
+       assigned-clocks = <&wiz0_refclk_dig>;
+       assigned-clock-parents = <&cmn_refclk1>;
+};
+
+&wiz1_pll1_refclk {
+       assigned-clocks = <&wiz1_pll1_refclk>;
+       assigned-clock-parents = <&cmn_refclk1>;
+};
+
+&wiz1_refclk_dig {
+       assigned-clocks = <&wiz1_refclk_dig>;
+       assigned-clock-parents = <&cmn_refclk1>;
+};
+
+&wiz2_pll1_refclk {
+       assigned-clocks = <&wiz2_pll1_refclk>;
+       assigned-clock-parents = <&cmn_refclk1>;
+};
+
+&wiz2_refclk_dig {
+       assigned-clocks = <&wiz2_refclk_dig>;
+       assigned-clock-parents = <&cmn_refclk1>;
+};
+
 &serdes0 {
+       assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
+       assigned-clock-parents = <&wiz0_pll1_refclk>;
+
        serdes0_pcie_link: link@0 {
                reg = <0>;
                cdns,num-lanes = <1>;
@@ -650,6 +684,9 @@
 };
 
 &serdes1 {
+       assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>;
+       assigned-clock-parents = <&wiz1_pll1_refclk>;
+
        serdes1_pcie_link: link@0 {
                reg = <0>;
                cdns,num-lanes = <2>;
@@ -660,6 +697,9 @@
 };
 
 &serdes2 {
+       assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>;
+       assigned-clock-parents = <&wiz2_pll1_refclk>;
+
        serdes2_pcie_link: link@0 {
                reg = <0>;
                cdns,num-lanes = <2>;