phy: qcom: edp: Postpone clk_set_rate until the PLL is up

When the platform was booted with the involved clocks enabled the
clk_set_rate() of the link and pixel clocks will perculate to the
children, which will fail to update because the PHY driver has just shut
down the PLL.

Postpone the clock rate updates until the PLL is back online to avoid
reconfiguring the clocks while the PLL is not ticking.

Fixes: f199223cb490 ("phy: qcom: Introduce new eDP PHY driver")
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220805154432.546740-1-bjorn.andersson@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy-qcom-edp.c
index de696108cf6ef2c671e3f8f7f809b7f15a0213d9..fc8ca0f3018df560d9332bba0bb01925612b707b 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-edp.c
+++ b/drivers/phy/qualcomm/phy-qcom-edp.c
@@ -410,31 +410,30 @@ static int qcom_edp_configure_pll(const struct qcom_edp *edp)
        return 0;
 }
 
-static int qcom_edp_set_vco_div(const struct qcom_edp *edp)
+static int qcom_edp_set_vco_div(const struct qcom_edp *edp, unsigned long *pixel_freq)
 {
        const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts;
-       unsigned long pixel_freq;
        u32 vco_div;
 
        switch (dp_opts->link_rate) {
        case 1620:
                vco_div = 0x1;
-               pixel_freq = 1620000000UL / 2;
+               *pixel_freq = 1620000000UL / 2;
                break;
 
        case 2700:
                vco_div = 0x1;
-               pixel_freq = 2700000000UL / 2;
+               *pixel_freq = 2700000000UL / 2;
                break;
 
        case 5400:
                vco_div = 0x2;
-               pixel_freq = 5400000000UL / 4;
+               *pixel_freq = 5400000000UL / 4;
                break;
 
        case 8100:
                vco_div = 0x0;
-               pixel_freq = 8100000000UL / 6;
+               *pixel_freq = 8100000000UL / 6;
                break;
 
        default:
@@ -444,9 +443,6 @@ static int qcom_edp_set_vco_div(const struct qcom_edp *edp)
 
        writel(vco_div, edp->edp + DP_PHY_VCO_DIV);
 
-       clk_set_rate(edp->dp_link_hw.clk, dp_opts->link_rate * 100000);
-       clk_set_rate(edp->dp_pixel_hw.clk, pixel_freq);
-
        return 0;
 }
 
@@ -455,6 +451,7 @@ static int qcom_edp_phy_power_on(struct phy *phy)
        const struct qcom_edp *edp = phy_get_drvdata(phy);
        const struct qcom_edp_cfg *cfg = edp->cfg;
        u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
+       unsigned long pixel_freq;
        u8 ldo_config;
        int timeout;
        int ret;
@@ -508,7 +505,7 @@ static int qcom_edp_phy_power_on(struct phy *phy)
        writel(0x01, edp->tx1 + TXn_TRAN_DRVR_EMP_EN);
        writel(0x04, edp->tx1 + TXn_TX_BAND);
 
-       ret = qcom_edp_set_vco_div(edp);
+       ret = qcom_edp_set_vco_div(edp, &pixel_freq);
        if (ret)
                return ret;
 
@@ -574,8 +571,15 @@ static int qcom_edp_phy_power_on(struct phy *phy)
 
        writel(0x19, edp->edp + DP_PHY_CFG);
 
-       return readl_poll_timeout(edp->edp + DP_PHY_STATUS,
-                                 val, val & BIT(1), 500, 10000);
+       ret = readl_poll_timeout(edp->edp + DP_PHY_STATUS,
+                                val, val & BIT(1), 500, 10000);
+       if (ret)
+               return ret;
+
+       clk_set_rate(edp->dp_link_hw.clk, edp->dp_opts.link_rate * 100000);
+       clk_set_rate(edp->dp_pixel_hw.clk, pixel_freq);
+
+       return 0;
 }
 
 static int qcom_edp_phy_power_off(struct phy *phy)