3680 has a few registers on other addresses.
Signed-off-by: Pontus Fuchs <pontus.fuchs@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
        writel(data, wcn->mmio + addr);
 }
 
+#define wcn36xx_dxe_write_register_x(wcn, reg, reg_data)                \
+do {                                                                    \
+       if (wcn->chip_version == WCN36XX_CHIP_3680)                      \
+               wcn36xx_dxe_write_register(wcn, reg ## _3680, reg_data); \
+       else                                                             \
+               wcn36xx_dxe_write_register(wcn, reg ## _3660, reg_data); \
+} while (0)                                                             \
+
 static void wcn36xx_dxe_read_register(struct wcn36xx *wcn, int addr, int *data)
 {
        *data = readl(wcn->mmio + addr);
 
        /* Setting interrupt path */
        reg_data = WCN36XX_DXE_CCU_INT;
-       wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_REG_CCU_INT, reg_data);
+       wcn36xx_dxe_write_register_x(wcn, WCN36XX_DXE_REG_CCU_INT, reg_data);
 
        /***************************************/
        /* Init descriptors for TX LOW channel */
 
 */
 
 /* DXE registers */
-#define WCN36XX_DXE_MEM_BASE                   0x03000000
 #define WCN36XX_DXE_MEM_REG                    0x202000
 
 #define WCN36XX_DXE_CCU_INT                    0xA0011
-#define WCN36XX_DXE_REG_CCU_INT                        0x200b10
+#define WCN36XX_DXE_REG_CCU_INT_3660           0x200b10
+#define WCN36XX_DXE_REG_CCU_INT_3680           0x2050dc
 
 /* TODO This must calculated properly but not hardcoded */
 #define WCN36XX_DXE_CTRL_TX_L                  0x328a44
 
        }
 }
 
+static void wcn36xx_detect_chip_version(struct wcn36xx *wcn)
+{
+       if (get_feat_caps(wcn->fw_feat_caps, DOT11AC)) {
+               wcn36xx_info("Chip is 3680\n");
+               wcn->chip_version = WCN36XX_CHIP_3680;
+       } else {
+               wcn36xx_info("Chip is 3660\n");
+               wcn->chip_version = WCN36XX_CHIP_3660;
+       }
+}
+
 static int wcn36xx_start(struct ieee80211_hw *hw)
 {
        struct wcn36xx *wcn = hw->priv;
                goto out_free_smd_buf;
        }
 
+       if (!wcn36xx_is_fw_version(wcn, 1, 2, 2, 24)) {
+               ret = wcn36xx_smd_feature_caps_exchange(wcn);
+               if (ret)
+                       wcn36xx_warn("Exchange feature caps failed\n");
+               else
+                       wcn36xx_feat_caps_info(wcn);
+       }
+
+       wcn36xx_detect_chip_version(wcn);
+
        /* DMA channel initialization */
        ret = wcn36xx_dxe_init(wcn);
        if (ret) {
 
        wcn36xx_debugfs_init(wcn);
 
-       if (!wcn36xx_is_fw_version(wcn, 1, 2, 2, 24)) {
-               ret = wcn36xx_smd_feature_caps_exchange(wcn);
-               if (ret)
-                       wcn36xx_warn("Exchange feature caps failed\n");
-               else
-                       wcn36xx_feat_caps_info(wcn);
-       }
        INIT_LIST_HEAD(&wcn->vif_list);
        return 0;
 
 
        u8                      fw_minor;
        u8                      fw_major;
        u32                     fw_feat_caps[WCN36XX_HAL_CAPS_SIZE];
+       u32                     chip_version;
 
        /* extra byte for the NULL termination */
        u8                      crm_version[WCN36XX_HAL_VERSION_LENGTH + 1];
 
 };
 
+#define WCN36XX_CHIP_3660      0
+#define WCN36XX_CHIP_3680      1
+
 static inline bool wcn36xx_is_fw_version(struct wcn36xx *wcn,
                                         u8 major,
                                         u8 minor,