clk: qcom: gcc-sm4450: Set delay for Venus CLK resets

Some Venus resets may require more time when toggling. Describe that.

The value was obtained on a best-guess basis: msm-5.4 being the base
kernel for this SoC and 4450 being somewhat close to 8350 which is known
to require a higher delay [1].

[1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/commit/dfe241edf23daf3c1ccbb79b02798965123fad98

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-7-c37eba13b5ce@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/drivers/clk/qcom/gcc-sm4450.c b/drivers/clk/qcom/gcc-sm4450.c
index 31abe2775fc8391fd577db68d3699981e0b7a112..ab8fb77d15a2082700fa64162ac43ac6c0ccac04 100644 (file)
--- a/drivers/clk/qcom/gcc-sm4450.c
+++ b/drivers/clk/qcom/gcc-sm4450.c
@@ -2791,8 +2791,8 @@ static const struct qcom_reset_map gcc_sm4450_resets[] = {
        [GCC_VENUS_BCR] = { 0xb601c },
        [GCC_VIDEO_BCR] = { 0x42000 },
        [GCC_VIDEO_VENUS_BCR] = { 0xb6000 },
-       [GCC_VENUS_CTL_AXI_CLK_ARES] = { 0x4201c, 2 },
-       [GCC_VIDEO_VENUS_CTL_CLK_ARES] = { 0xb6038, 2 },
+       [GCC_VENUS_CTL_AXI_CLK_ARES] = { .reg = 0x4201c, .bit = 2, .udelay = 400 },
+       [GCC_VIDEO_VENUS_CTL_CLK_ARES] = { .reg = 0xb6038, .bit = 2, .udelay = 400 },
 };
 
 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {