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drm/i915/ringbuffer: Clear semaphore sync registers on ring init
author
Chris Wilson
<chris@chris-wilson.co.uk>
Mon, 3 Dec 2018 11:36:56 +0000
(11:36 +0000)
committer
Chris Wilson
<chris@chris-wilson.co.uk>
Mon, 3 Dec 2018 12:25:42 +0000
(12:25 +0000)
Ensure that the sync registers are cleared every time we restart the
ring to avoid stale values from creeping in from random neutrinos.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108888
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link:
https://patchwork.freedesktop.org/patch/msgid/20181203113701.12106-3-chris@chris-wilson.co.uk
drivers/gpu/drm/i915/intel_ringbuffer.c
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diff --git
a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 28ae1e436ea638cb93a302c1152440a16f75c365..d81eaf5f6b3e1e375d752606c1dce3e86f39a955 100644
(file)
--- a/
drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/
drivers/gpu/drm/i915/intel_ringbuffer.c
@@
-529,6
+529,13
@@
static int init_ring_common(struct intel_engine_cs *engine)
intel_engine_reset_breadcrumbs(engine);
+ if (HAS_LEGACY_SEMAPHORES(engine->i915)) {
+ I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
+ I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
+ if (HAS_VEBOX(dev_priv))
+ I915_WRITE(RING_SYNC_2(engine->mmio_base), 0);
+ }
+
/* Enforce ordering by reading HEAD register back */
I915_READ_HEAD(engine);