arm64: dts: mediatek: mt8186: Wire up GPU voltage/frequency scaling

Add the GPU's OPP table. This is from the downstream ChromeOS kernel,
adapted to the new upstream opp-supported-hw binning format. Also add
dynamic-power-coefficient for the GPU.

Also add label for mfg1 power domain. This is to be used at the board
level to add a regulator supply for the power domain.

Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230609072906.2784594-5-wenst@chromium.org
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index 3762a70ccafb8e42f4e478992f26a6149c73ce8d..f04ae70c470aa3f409579187c12ac9eac77b4cd9 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -647,6 +647,142 @@
                clock-output-names = "clk32k";
        };
 
+       gpu_opp_table: opp-table-gpu {
+               compatible = "operating-points-v2";
+
+               opp-299000000 {
+                       opp-hz = /bits/ 64 <299000000>;
+                       opp-microvolt = <612500>;
+                       opp-supported-hw = <0xff>;
+               };
+
+               opp-332000000 {
+                       opp-hz = /bits/ 64 <332000000>;
+                       opp-microvolt = <625000>;
+                       opp-supported-hw = <0xff>;
+               };
+
+               opp-366000000 {
+                       opp-hz = /bits/ 64 <366000000>;
+                       opp-microvolt = <637500>;
+                       opp-supported-hw = <0xff>;
+               };
+
+               opp-400000000 {
+                       opp-hz = /bits/ 64 <400000000>;
+                       opp-microvolt = <643750>;
+                       opp-supported-hw = <0xff>;
+               };
+
+               opp-434000000 {
+                       opp-hz = /bits/ 64 <434000000>;
+                       opp-microvolt = <656250>;
+                       opp-supported-hw = <0xff>;
+               };
+
+               opp-484000000 {
+                       opp-hz = /bits/ 64 <484000000>;
+                       opp-microvolt = <668750>;
+                       opp-supported-hw = <0xff>;
+               };
+
+               opp-535000000 {
+                       opp-hz = /bits/ 64 <535000000>;
+                       opp-microvolt = <687500>;
+                       opp-supported-hw = <0xff>;
+               };
+
+               opp-586000000 {
+                       opp-hz = /bits/ 64 <586000000>;
+                       opp-microvolt = <700000>;
+                       opp-supported-hw = <0xff>;
+               };
+
+               opp-637000000 {
+                       opp-hz = /bits/ 64 <637000000>;
+                       opp-microvolt = <712500>;
+                       opp-supported-hw = <0xff>;
+               };
+
+               opp-690000000 {
+                       opp-hz = /bits/ 64 <690000000>;
+                       opp-microvolt = <737500>;
+                       opp-supported-hw = <0xff>;
+               };
+
+               opp-743000000 {
+                       opp-hz = /bits/ 64 <743000000>;
+                       opp-microvolt = <756250>;
+                       opp-supported-hw = <0xff>;
+               };
+
+               opp-796000000 {
+                       opp-hz = /bits/ 64 <796000000>;
+                       opp-microvolt = <781250>;
+                       opp-supported-hw = <0xff>;
+               };
+
+               opp-850000000 {
+                       opp-hz = /bits/ 64 <850000000>;
+                       opp-microvolt = <800000>;
+                       opp-supported-hw = <0xff>;
+               };
+
+               opp-900000000-3 {
+                       opp-hz = /bits/ 64 <900000000>;
+                       opp-microvolt = <850000>;
+                       opp-supported-hw = <0x8>;
+               };
+
+               opp-900000000-4 {
+                       opp-hz = /bits/ 64 <900000000>;
+                       opp-microvolt = <837500>;
+                       opp-supported-hw = <0x10>;
+               };
+
+               opp-900000000-5 {
+                       opp-hz = /bits/ 64 <900000000>;
+                       opp-microvolt = <825000>;
+                       opp-supported-hw = <0x30>;
+               };
+
+               opp-950000000-3 {
+                       opp-hz = /bits/ 64 <950000000>;
+                       opp-microvolt = <900000>;
+                       opp-supported-hw = <0x8>;
+               };
+
+               opp-950000000-4 {
+                       opp-hz = /bits/ 64 <950000000>;
+                       opp-microvolt = <875000>;
+                       opp-supported-hw = <0x10>;
+               };
+
+               opp-950000000-5 {
+                       opp-hz = /bits/ 64 <950000000>;
+                       opp-microvolt = <850000>;
+                       opp-supported-hw = <0x30>;
+               };
+
+               opp-1000000000-3 {
+                       opp-hz = /bits/ 64 <1000000000>;
+                       opp-microvolt = <950000>;
+                       opp-supported-hw = <0x8>;
+               };
+
+               opp-1000000000-4 {
+                       opp-hz = /bits/ 64 <1000000000>;
+                       opp-microvolt = <912500>;
+                       opp-supported-hw = <0x10>;
+               };
+
+               opp-1000000000-5 {
+                       opp-hz = /bits/ 64 <1000000000>;
+                       opp-microvolt = <875000>;
+                       opp-supported-hw = <0x30>;
+               };
+       };
+
        pmu-a55 {
                compatible = "arm,cortex-a55-pmu";
                interrupt-parent = <&gic>;
@@ -765,7 +901,7 @@
                                        #size-cells = <0>;
                                        #power-domain-cells = <1>;
 
-                                       power-domain@MT8186_POWER_DOMAIN_MFG1 {
+                                       mfg1: power-domain@MT8186_POWER_DOMAIN_MFG1 {
                                                reg = <MT8186_POWER_DOMAIN_MFG1>;
                                                mediatek,infracfg = <&infracfg_ao>;
                                                #address-cells = <1>;
@@ -1558,6 +1694,8 @@
                        #cooling-cells = <2>;
                        nvmem-cells = <&gpu_speedbin>;
                        nvmem-cell-names = "speed-bin";
+                       operating-points-v2 = <&gpu_opp_table>;
+                       dynamic-power-coefficient = <4687>;
                        status = "disabled";
                };