Loongson-3A R2.1 is the bugfix revision of Loongson-3A R2.
All Loongson-3 CPU family:
Code-name         Brand-name       PRId
Loongson-3A R1    Loongson-3A1000  0x6305
Loongson-3A R2    Loongson-3A2000  0x6308
Loongson-3A R2.1  Loongson-3A2000  0x630c
Loongson-3A R3    Loongson-3A3000  0x6309
Loongson-3A R3.1  Loongson-3A3000  0x630d
Loongson-3B R1    Loongson-3B1000  0x6306
Loongson-3B R2    Loongson-3B1500  0x6307
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/21128/
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <james.hogan@mips.com>
Cc: Steven J . Hill <Steven.Hill@cavium.com>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
 #define PRID_REV_LOONGSON3A_R1         0x0005
 #define PRID_REV_LOONGSON3B_R1         0x0006
 #define PRID_REV_LOONGSON3B_R2         0x0007
-#define PRID_REV_LOONGSON3A_R2         0x0008
+#define PRID_REV_LOONGSON3A_R2_0       0x0008
 #define PRID_REV_LOONGSON3A_R3_0       0x0009
+#define PRID_REV_LOONGSON3A_R2_1       0x000c
 #define PRID_REV_LOONGSON3A_R3_1       0x000d
 
 /*
 
        /* Enable STFill Buffer */
        mfc0    t0, CP0_PRID
        andi    t0, (PRID_IMP_MASK | PRID_REV_MASK)
-       slti    t0, (PRID_IMP_LOONGSON_64 | PRID_REV_LOONGSON3A_R2)
+       slti    t0, (PRID_IMP_LOONGSON_64 | PRID_REV_LOONGSON3A_R2_0)
        bnez    t0, 1f
        mfc0    t0, CP0_CONFIG6
        or      t0, 0x100
        /* Enable STFill Buffer */
        mfc0    t0, CP0_PRID
        andi    t0, (PRID_IMP_MASK | PRID_REV_MASK)
-       slti    t0, (PRID_IMP_LOONGSON_64 | PRID_REV_LOONGSON3A_R2)
+       slti    t0, (PRID_IMP_LOONGSON_64 | PRID_REV_LOONGSON3A_R2_0)
        bnez    t0, 1f
        mfc0    t0, CP0_CONFIG6
        or      t0, 0x100
 
        switch (c->processor_id & PRID_IMP_MASK) {
        case PRID_IMP_LOONGSON_64:  /* Loongson-2/3 */
                switch (c->processor_id & PRID_REV_MASK) {
-               case PRID_REV_LOONGSON3A_R2:
+               case PRID_REV_LOONGSON3A_R2_0:
+               case PRID_REV_LOONGSON3A_R2_1:
                        c->cputype = CPU_LOONGSON3;
                        __cpu_name[cpu] = "ICT Loongson-3";
                        set_elf_platform(cpu, "loongson3a");
 
                cpu_wait = r4k_wait;
                break;
        case CPU_LOONGSON3:
-               if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_LOONGSON3A_R2)
+               if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_LOONGSON3A_R2_0)
                        cpu_wait = r4k_wait;
                break;
 
 
                        cpu_clock_freq = 797000000;
                        break;
                case PRID_REV_LOONGSON3A_R1:
-               case PRID_REV_LOONGSON3A_R2:
+               case PRID_REV_LOONGSON3A_R2_0:
+               case PRID_REV_LOONGSON3A_R2_1:
                case PRID_REV_LOONGSON3A_R3_0:
                case PRID_REV_LOONGSON3A_R3_1:
                        cpu_clock_freq = 900000000;
 
                play_dead_at_ckseg1 =
                        (void *)CKSEG1ADDR((unsigned long)loongson3a_r1_play_dead);
                break;
-       case PRID_REV_LOONGSON3A_R2:
+       case PRID_REV_LOONGSON3A_R2_0:
+       case PRID_REV_LOONGSON3A_R2_1:
        case PRID_REV_LOONGSON3A_R3_0:
        case PRID_REV_LOONGSON3A_R3_1:
                play_dead_at_ckseg1 =
 
                                          c->dcache.ways *
                                          c->dcache.linesz;
                c->dcache.waybit = 0;
-               if ((prid & PRID_REV_MASK) >= PRID_REV_LOONGSON3A_R2)
+               if ((prid & PRID_REV_MASK) >= PRID_REV_LOONGSON3A_R2_0)
                        c->options |= MIPS_CPU_PREFETCH;
                break;
 
 
        case PRID_REV_LOONGSON3A_R1:
                reg = (reg >> 8) & 0xff;
                break;
-       case PRID_REV_LOONGSON3A_R2:
        case PRID_REV_LOONGSON3B_R1:
        case PRID_REV_LOONGSON3B_R2:
+       case PRID_REV_LOONGSON3A_R2_0:
+       case PRID_REV_LOONGSON3A_R2_1:
                reg = ((reg >> 8) & 0xff) - 100;
                break;
        case PRID_REV_LOONGSON3A_R3_0: