arm64: dts: layerscape: correct watchdog clocks for LS1088A

On LS1088A, watchdog clk are divided by 16, correct it in dts.

Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index 28f44ac96ca78aa427d41640e70a6a738a6087b0..ff5805206a289c9e11d124d0dc2e155d8aee8de4 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -675,56 +675,56 @@
                cluster1_core0_watchdog: wdt@c000000 {
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc000000 0x0 0x1000>;
-                       clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+                       clocks = <&clockgen 4 15>, <&clockgen 4 15>;
                        clock-names = "wdog_clk", "apb_pclk";
                };
 
                cluster1_core1_watchdog: wdt@c010000 {
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc010000 0x0 0x1000>;
-                       clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+                       clocks = <&clockgen 4 15>, <&clockgen 4 15>;
                        clock-names = "wdog_clk", "apb_pclk";
                };
 
                cluster1_core2_watchdog: wdt@c020000 {
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc020000 0x0 0x1000>;
-                       clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+                       clocks = <&clockgen 4 15>, <&clockgen 4 15>;
                        clock-names = "wdog_clk", "apb_pclk";
                };
 
                cluster1_core3_watchdog: wdt@c030000 {
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc030000 0x0 0x1000>;
-                       clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+                       clocks = <&clockgen 4 15>, <&clockgen 4 15>;
                        clock-names = "wdog_clk", "apb_pclk";
                };
 
                cluster2_core0_watchdog: wdt@c100000 {
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc100000 0x0 0x1000>;
-                       clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+                       clocks = <&clockgen 4 15>, <&clockgen 4 15>;
                        clock-names = "wdog_clk", "apb_pclk";
                };
 
                cluster2_core1_watchdog: wdt@c110000 {
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc110000 0x0 0x1000>;
-                       clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+                       clocks = <&clockgen 4 15>, <&clockgen 4 15>;
                        clock-names = "wdog_clk", "apb_pclk";
                };
 
                cluster2_core2_watchdog: wdt@c120000 {
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc120000 0x0 0x1000>;
-                       clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+                       clocks = <&clockgen 4 15>, <&clockgen 4 15>;
                        clock-names = "wdog_clk", "apb_pclk";
                };
 
                cluster2_core3_watchdog: wdt@c130000 {
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc130000 0x0 0x1000>;
-                       clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+                       clocks = <&clockgen 4 15>, <&clockgen 4 15>;
                        clock-names = "wdog_clk", "apb_pclk";
                };