drm/i915: merge gen checks to use range

Instead of using IS_GEN() for consecutive gen checks, let's pass the
range to IS_GEN_RANGE(). By code inspection these were the ranges deemed
necessary for spatch:

@@
expression e;
@@
(
- IS_GEN(e, 3) || IS_GEN(e, 2)
+ IS_GEN_RANGE(e, 2, 3)
|
- IS_GEN(e, 3) || IS_GEN(e, 4)
+ IS_GEN_RANGE(e, 3, 4)
|
- IS_GEN(e, 5) || IS_GEN(e, 6)
+ IS_GEN_RANGE(e, 5, 6)
|
- IS_GEN(e, 6) || IS_GEN(e, 7)
+ IS_GEN_RANGE(e, 6, 7)
|
- IS_GEN(e, 7) || IS_GEN(e, 8)
+ IS_GEN_RANGE(e, 7, 8)
|
- IS_GEN(e, 8) || IS_GEN(e, 9)
+ IS_GEN_RANGE(e, 8, 9)
|
- IS_GEN(e, 10) || IS_GEN(e, 9)
+ IS_GEN_RANGE(e, 9, 10)
|
- IS_GEN(e, 9) || IS_GEN(e, 10)
+ IS_GEN_RANGE(e, 9, 10)
)

After conversion, checking we don't have any missing IS_GEN_RANGE() ||
IS_GEN() was also done.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181212181044.15886-3-lucas.demarchi@intel.com

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 2b52c91113b340cb2eaa21697ccf265946b83bf6..ed44e30f875efaf5cb8fdebac074f974b1dbebc6 100644 (file)
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2040,7 +2040,7 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
        seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
                   swizzle_string(dev_priv->mm.bit_6_swizzle_y));
 
-       if (IS_GEN(dev_priv, 3) || IS_GEN(dev_priv, 4)) {
+       if (IS_GEN_RANGE(dev_priv, 3, 4)) {
                seq_printf(m, "DDC = 0x%08x\n",
                           I915_READ(DCC));
                seq_printf(m, "DDC2 = 0x%08x\n",
@@ -4274,7 +4274,7 @@ i915_cache_sharing_get(void *data, u64 *val)
        struct drm_i915_private *dev_priv = data;
        u32 snpcr;
 
-       if (!(IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)))
+       if (!(IS_GEN_RANGE(dev_priv, 6, 7)))
                return -ENODEV;
 
        intel_runtime_pm_get(dev_priv);
@@ -4294,7 +4294,7 @@ i915_cache_sharing_set(void *data, u64 val)
        struct drm_i915_private *dev_priv = data;
        u32 snpcr;
 
-       if (!(IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)))
+       if (!(IS_GEN_RANGE(dev_priv, 6, 7)))
                return -ENODEV;
 
        if (val > 3)

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 4477631d26361a5aac6149fba0e5e8fd1e71a3a9..63df41d933793ee0aca876fa41203bc5de129f4f 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1753,7 +1753,7 @@ static void capture_reg_state(struct i915_gpu_state *error)
                error->ccid = I915_READ(CCID);
 
        /* 3: Feature specific registers */
-       if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)) {
+       if (IS_GEN_RANGE(dev_priv, 6, 7)) {
                error->gam_ecochk = I915_READ(GAM_ECOCHK);
                error->gac_eco = I915_READ(GAC_ECO_BITS);
        }

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 6c799232044399c9b57d4dbc5b55f3758c5ea63c..4288c0e02f0ccc549a16c702d82afbbcda47756c 100644 (file)
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -3415,7 +3415,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
                dev_priv->perf.oa.ops.read = gen8_oa_read;
                dev_priv->perf.oa.ops.oa_hw_tail_read = gen8_oa_hw_tail_read;
 
-               if (IS_GEN(dev_priv, 8) || IS_GEN(dev_priv, 9)) {
+               if (IS_GEN_RANGE(dev_priv, 8, 9)) {
                        dev_priv->perf.oa.ops.is_valid_b_counter_reg =
                                gen7_is_valid_b_counter_addr;
                        dev_priv->perf.oa.ops.is_valid_mux_reg =

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index bf4fd739b68c4bd99a8475df93b9b65b89341b3e..0a41e58d61defc5c3deeb94a22b8db9c437b7971 100644 (file)
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -322,7 +322,7 @@ intel_crt_mode_valid(struct drm_connector *connector,
                 * DAC limit supposedly 355 MHz.
                 */
                max_clock = 270000;
-       else if (IS_GEN(dev_priv, 3) || IS_GEN(dev_priv, 4))
+       else if (IS_GEN_RANGE(dev_priv, 3, 4))
                max_clock = 400000;
        else
                max_clock = 350000;

diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 8627b9a6bff4eadc0ab3ee9b8cb027ce11c25cb5..eccb30a68b104c9ef6bab9d1468cd37660037969 100644 (file)
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -787,7 +787,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
                DRM_INFO("Display disabled (module parameter)\n");
                info->num_pipes = 0;
        } else if (HAS_DISPLAY(dev_priv) &&
-                  (IS_GEN(dev_priv, 7) || IS_GEN(dev_priv, 8)) &&
+                  (IS_GEN_RANGE(dev_priv, 7, 8)) &&
                   HAS_PCH_SPLIT(dev_priv)) {
                u32 fuse_strap = I915_READ(FUSE_STRAP);
                u32 sfuse_strap = I915_READ(SFUSE_STRAP);

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b9e8a9898983b7ecea5988a29205dea4514ceafe..2c3f3f68d506bbbcd723d8f46ab02d8ac5ee3324 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10815,7 +10815,7 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
         * the w/a on all three platforms.
         */
        if (plane->id == PLANE_SPRITE0 &&
-           (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6) ||
+           (IS_GEN_RANGE(dev_priv, 5, 6) ||
             IS_IVYBRIDGE(dev_priv)) &&
            (turn_on || (!needs_scaling(old_plane_state) &&
                         needs_scaling(to_intel_plane_state(plane_state)))))

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 8ff794db7881d08b9948d05500c54d028c703686..66d0ad9c36c4c44ba7787dbdeba334db7a58a40e 100644 (file)
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -438,7 +438,7 @@ void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno)
         * the semaphore value, then when the seqno moves backwards all
         * future waits will complete instantly (causing rendering corruption).
         */
-       if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)) {
+       if (IS_GEN_RANGE(dev_priv, 6, 7)) {
                I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
                I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
                if (HAS_VEBOX(dev_priv))

diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c b/drivers/gpu/drm/i915/intel_fifo_underrun.c
index ff2743ccbecec82ca643ee6cda5b8a5899a01387..9b39975c8389a6d3e15aab2736bd7bd70ab1b10d 100644 (file)
--- a/drivers/gpu/drm/i915/intel_fifo_underrun.c
+++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c
@@ -260,7 +260,7 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 
        if (HAS_GMCH_DISPLAY(dev_priv))
                i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old);
-       else if (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6))
+       else if (IS_GEN_RANGE(dev_priv, 5, 6))
                ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
        else if (IS_GEN(dev_priv, 7))
                ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old);

diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c b/drivers/gpu/drm/i915/intel_pipe_crc.c
index 9e870caf8104b625b4132fd392be2c5587a57e05..bdabcfab8090f75a8262e47ee9d05ec15b9aa25e 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pipe_crc.c
+++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
@@ -433,7 +433,7 @@ static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv,
                return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
        else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
                return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
-       else if (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6))
+       else if (IS_GEN_RANGE(dev_priv, 5, 6))
                return ilk_pipe_crc_ctl_reg(source, val);
        else
                return ivb_pipe_crc_ctl_reg(dev_priv, pipe, source, val, set_wa);
@@ -550,7 +550,7 @@ intel_is_valid_crc_source(struct drm_i915_private *dev_priv,
                return i9xx_crc_source_valid(dev_priv, source);
        else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
                return vlv_crc_source_valid(dev_priv, source);
-       else if (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6))
+       else if (IS_GEN_RANGE(dev_priv, 5, 6))
                return ilk_crc_source_valid(dev_priv, source);
        else
                return ivb_crc_source_valid(dev_priv, source);

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index c6eb053a8fadf6c8785a5a4e4ef7f63dda3e2fa8..ec6dde2e59ebfd3a400d33184ab2dca23f8aff3d 100644 (file)
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -528,7 +528,7 @@ check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
        if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
                ret |= vlv_check_for_unclaimed_mmio(dev_priv);
 
-       if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7))
+       if (IS_GEN_RANGE(dev_priv, 6, 7))
                ret |= gen6_check_for_fifo_debug(dev_priv);
 
        return ret;
@@ -556,7 +556,7 @@ static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
                dev_priv->uncore.funcs.force_wake_get(dev_priv,
                                                      restore_forcewake);
 
-               if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7))
+               if (IS_GEN_RANGE(dev_priv, 6, 7))
                        dev_priv->uncore.fifo_count =
                                fifo_free_entries(dev_priv);
                spin_unlock_irq(&dev_priv->uncore.lock);
@@ -1437,7 +1437,7 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
                                       FORCEWAKE_MEDIA_VEBOX_GEN11(i),
                                       FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i));
                }
-       } else if (IS_GEN(dev_priv, 10) || IS_GEN(dev_priv, 9)) {
+       } else if (IS_GEN_RANGE(dev_priv, 9, 10)) {
                dev_priv->uncore.funcs.force_wake_get =
                        fw_domains_get_with_fallback;
                dev_priv->uncore.funcs.force_wake_put = fw_domains_put;