MIPS: regdefs.h: Define a set of register numbers

Define a set of register numbers with their symbolic
names to help with uasm code.

All names are prefixed by GPR_ to prevent naming
clash.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

diff --git a/arch/mips/include/asm/regdef.h b/arch/mips/include/asm/regdef.h
index 87ba7be1a84715d5f0aab47ba9996d08c4ed8448..236051364f78e2e7586a3fc2097e0a55de2de36e 100644 (file)
--- a/arch/mips/include/asm/regdef.h
+++ b/arch/mips/include/asm/regdef.h
@@ -14,6 +14,95 @@
 
 #include <asm/sgidefs.h>
 
+#if _MIPS_SIM == _MIPS_SIM_ABI32
+
+/*
+ * General purpose register numbers for 32 bit ABI
+ */
+#define GPR_ZERO       0       /* wired zero */
+#define GPR_AT 1       /* assembler temp */
+#define GPR_V0 2       /* return value */
+#define GPR_V1 3
+#define GPR_A0 4       /* argument registers */
+#define GPR_A1 5
+#define GPR_A2 6
+#define GPR_A3 7
+#define GPR_T0 8       /* caller saved */
+#define GPR_T1 9
+#define GPR_T2 10
+#define GPR_T3 11
+#define GPR_T4 12
+#define GPR_TA0        12
+#define GPR_T5 13
+#define GPR_TA1        13
+#define GPR_T6 14
+#define GPR_TA2        14
+#define GPR_T7 15
+#define GPR_TA3        15
+#define GPR_S0 16      /* callee saved */
+#define GPR_S1 17
+#define GPR_S2 18
+#define GPR_S3 19
+#define GPR_S4 20
+#define GPR_S5 21
+#define GPR_S6 22
+#define GPR_S7 23
+#define GPR_T8 24      /* caller saved */
+#define GPR_T9 25
+#define GPR_JP 25      /* PIC jump register */
+#define GPR_K0 26      /* kernel scratch */
+#define GPR_K1 27
+#define GPR_GP 28      /* global pointer */
+#define GPR_SP 29      /* stack pointer */
+#define GPR_FP 30      /* frame pointer */
+#define GPR_S8 30      /* same like fp! */
+#define GPR_RA 31      /* return address */
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
+
+#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
+
+#define GPR_ZERO       0       /* wired zero */
+#define GPR_AT 1       /* assembler temp */
+#define GPR_V0 2       /* return value - caller saved */
+#define GPR_V1 3
+#define GPR_A0 4       /* argument registers */
+#define GPR_A1 5
+#define GPR_A2 6
+#define GPR_A3 7
+#define GPR_A4 8       /* arg reg 64 bit; caller saved in 32 bit */
+#define GPR_TA0        8
+#define GPR_A5 9
+#define GPR_TA1        9
+#define GPR_A6 10
+#define GPR_TA2        10
+#define GPR_A7 11
+#define GPR_TA3        11
+#define GPR_T0 12      /* caller saved */
+#define GPR_T1 13
+#define GPR_T2 14
+#define GPR_T3 15
+#define GPR_S0 16      /* callee saved */
+#define GPR_S1 17
+#define GPR_S2 18
+#define GPR_S3 19
+#define GPR_S4 20
+#define GPR_S5 21
+#define GPR_S6 22
+#define GPR_S7 23
+#define GPR_T8 24      /* caller saved */
+#define GPR_T9 25      /* callee address for PIC/temp */
+#define GPR_JP 25      /* PIC jump register */
+#define GPR_K0 26      /* kernel temporary */
+#define GPR_K1 27
+#define GPR_GP 28      /* global pointer - caller saved for PIC */
+#define GPR_SP 29      /* stack pointer */
+#define GPR_FP 30      /* frame pointer */
+#define GPR_S8 30      /* callee saved */
+#define GPR_RA 31      /* return address */
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */
+
 #ifdef __ASSEMBLY__
 #if _MIPS_SIM == _MIPS_SIM_ABI32