RISC-V: KVM: Allow Zvfh[min] extensions for Guest/VM
authorAnup Patel <apatel@ventanamicro.com>
Mon, 27 Nov 2023 16:56:05 +0000 (22:26 +0530)
committerAnup Patel <anup@brainfault.org>
Fri, 19 Jan 2024 03:50:11 +0000 (09:20 +0530)
We extend the KVM ISA extension ONE_REG interface to allow KVM
user space to detect and enable Zvfh[min] extensions for Guest/VM.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
arch/riscv/include/uapi/asm/kvm.h
arch/riscv/kvm/vcpu_onereg.c

index 95e4d5a1793e745d6ac1a90bd240f96f5ac4572f..7d07722aa1aaf12a1135687f3c1d3c42a9999fc6 100644 (file)
@@ -163,6 +163,8 @@ enum KVM_RISCV_ISA_EXT_ID {
        KVM_RISCV_ISA_EXT_ZFH,
        KVM_RISCV_ISA_EXT_ZFHMIN,
        KVM_RISCV_ISA_EXT_ZIHINTNTL,
+       KVM_RISCV_ISA_EXT_ZVFH,
+       KVM_RISCV_ISA_EXT_ZVFHMIN,
        KVM_RISCV_ISA_EXT_MAX,
 };
 
index deceaa6f9cfa228da7e72755e7516f422ee47446..707d9d9883c856b4a196132be6f1d33d39271761 100644 (file)
@@ -67,6 +67,8 @@ static const unsigned long kvm_isa_ext_arr[] = {
        KVM_ISA_EXT_ARR(ZKT),
        KVM_ISA_EXT_ARR(ZVBB),
        KVM_ISA_EXT_ARR(ZVBC),
+       KVM_ISA_EXT_ARR(ZVFH),
+       KVM_ISA_EXT_ARR(ZVFHMIN),
        KVM_ISA_EXT_ARR(ZVKB),
        KVM_ISA_EXT_ARR(ZVKG),
        KVM_ISA_EXT_ARR(ZVKNED),
@@ -139,6 +141,8 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext)
        case KVM_RISCV_ISA_EXT_ZKT:
        case KVM_RISCV_ISA_EXT_ZVBB:
        case KVM_RISCV_ISA_EXT_ZVBC:
+       case KVM_RISCV_ISA_EXT_ZVFH:
+       case KVM_RISCV_ISA_EXT_ZVFHMIN:
        case KVM_RISCV_ISA_EXT_ZVKB:
        case KVM_RISCV_ISA_EXT_ZVKG:
        case KVM_RISCV_ISA_EXT_ZVKNED: