arm64: dts: mediatek: mt6795: Add cpu-map and L2 cache

This SoC is HMP and has two clusters with four Cortex-A53 cores each:
declare a cpu map and, while at it, also add the next-level-cache
properties.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220609112303.117928-3-angelogioacchino.delregno@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index 167f90bd991aca1f46cf6ee1db3ada8b157070da..1456b9035336af5d97470ff817752afb6758e9f5 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -34,6 +34,7 @@
                        compatible = "arm,cortex-a53";
                        enable-method = "psci";
                        reg = <0x000>;
+                       next-level-cache = <&l2_0>;
                };
 
                cpu1: cpu@1 {
@@ -41,6 +42,7 @@
                        compatible = "arm,cortex-a53";
                        enable-method = "psci";
                        reg = <0x001>;
+                       next-level-cache = <&l2_0>;
                };
 
                cpu2: cpu@2 {
@@ -48,6 +50,7 @@
                        compatible = "arm,cortex-a53";
                        enable-method = "psci";
                        reg = <0x002>;
+                       next-level-cache = <&l2_0>;
                };
 
                cpu3: cpu@3 {
@@ -55,6 +58,7 @@
                        compatible = "arm,cortex-a53";
                        enable-method = "psci";
                        reg = <0x003>;
+                       next-level-cache = <&l2_0>;
                };
 
                cpu4: cpu@100 {
@@ -62,6 +66,7 @@
                        compatible = "arm,cortex-a53";
                        enable-method = "psci";
                        reg = <0x100>;
+                       next-level-cache = <&l2_1>;
                };
 
                cpu5: cpu@101 {
@@ -69,6 +74,7 @@
                        compatible = "arm,cortex-a53";
                        enable-method = "psci";
                        reg = <0x101>;
+                       next-level-cache = <&l2_1>;
                };
 
                cpu6: cpu@102 {
@@ -76,6 +82,7 @@
                        compatible = "arm,cortex-a53";
                        enable-method = "psci";
                        reg = <0x102>;
+                       next-level-cache = <&l2_1>;
                };
 
                cpu7: cpu@103 {
@@ -83,6 +90,55 @@
                        compatible = "arm,cortex-a53";
                        enable-method = "psci";
                        reg = <0x103>;
+                       next-level-cache = <&l2_1>;
+               };
+
+               cpu-map {
+                       cluster0 {
+                               core0 {
+                                       cpu = <&cpu0>;
+                               };
+
+                               core1 {
+                                       cpu = <&cpu1>;
+                               };
+
+                               core2 {
+                                       cpu = <&cpu2>;
+                               };
+
+                               core3 {
+                                       cpu = <&cpu3>;
+                               };
+                       };
+
+                       cluster1 {
+                               core0 {
+                                       cpu = <&cpu4>;
+                               };
+
+                               core1 {
+                                       cpu = <&cpu5>;
+                               };
+
+                               core2 {
+                                       cpu = <&cpu6>;
+                               };
+
+                               core3 {
+                                       cpu = <&cpu7>;
+                               };
+                       };
+               };
+
+               l2_0: l2-cache0 {
+                       compatible = "cache";
+                       cache-level = <2>;
+               };
+
+               l2_1: l2-cache1 {
+                       compatible = "cache";
+                       cache-level = <2>;
                };
        };