bus: mhi: Ensure correct ring update ordering with memory barrier

The ring element data, though being part of coherent memory, still need
to be performed before updating the ring context to point to this new
element. That can be guaranteed with a memory barrier (dma_wmb).

Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

diff --git a/drivers/bus/mhi/core/main.c b/drivers/bus/mhi/core/main.c
index 9b425402767ce7dadf92b4bcb3c902c841099d7d..8576b0f03f2cd5d5b723b6a83d130e3f506d3f7c 100644 (file)
--- a/drivers/bus/mhi/core/main.c
+++ b/drivers/bus/mhi/core/main.c
@@ -111,7 +111,14 @@ void mhi_ring_chan_db(struct mhi_controller *mhi_cntrl,
        dma_addr_t db;
 
        db = ring->iommu_base + (ring->wp - ring->base);
+
+       /*
+        * Writes to the new ring element must be visible to the hardware
+        * before letting h/w know there is new element to fetch.
+        */
+       dma_wmb();
        *ring->ctxt_wp = db;
+
        mhi_chan->db_cfg.process_db(mhi_cntrl, &mhi_chan->db_cfg,
                                    ring->db_addr, db);
 }