media: rkisp1: Program RKISP1_CIF_MI_SP_Y_PIC_SIZE register
authorLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Thu, 27 Apr 2023 08:43:17 +0000 (11:43 +0300)
committerHans Verkuil <hverkuil-cisco@xs4all.nl>
Thu, 12 Oct 2023 07:46:37 +0000 (09:46 +0200)
The self path has a Y_PIC_SIZE register that needs to be programmed to
the total number of pixels, including the stride. This isn't done by the
driver, fix it.

While at it, reorder the register write order to sort them by address.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c

index 3c1e2c1a8bbe944cff103b9c28d8dfb782468dd4..c6d7e01c89494a94e3ee741e1b673148c6c64f19 100644 (file)
@@ -479,9 +479,11 @@ static void rkisp1_sp_config(struct rkisp1_capture *cap)
        rkisp1_write(rkisp1, cap->config->mi.cr_size_init,
                     rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CR));
 
+       rkisp1_write(rkisp1, RKISP1_CIF_MI_SP_Y_LLENGTH, cap->sp_y_stride);
        rkisp1_write(rkisp1, RKISP1_CIF_MI_SP_Y_PIC_WIDTH, pixm->width);
        rkisp1_write(rkisp1, RKISP1_CIF_MI_SP_Y_PIC_HEIGHT, pixm->height);
-       rkisp1_write(rkisp1, RKISP1_CIF_MI_SP_Y_LLENGTH, cap->sp_y_stride);
+       rkisp1_write(rkisp1, RKISP1_CIF_MI_SP_Y_PIC_SIZE,
+                    cap->sp_y_stride * pixm->height);
 
        rkisp1_irq_frame_end_enable(cap);