};
 };
 
+&nand0 {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_nand0_default>;
+       arasan,has-mdma;
+
+       nand@0 {
+               reg = <0x0>;
+               #address-cells = <0x2>;
+               #size-cells = <0x1>;
+               nand-ecc-mode = "soft";
+               nand-ecc-algo = "bch";
+               nand-rb = <0>;
+               label = "main-storage-0";
+       };
+       nand@1 {
+               reg = <0x1>;
+               #address-cells = <0x2>;
+               #size-cells = <0x1>;
+               nand-ecc-mode = "soft";
+               nand-ecc-algo = "bch";
+               nand-rb = <0>;
+               label = "main-storage-1";
+       };
+};
+
 &pinctrl0 {
        status = "okay";
        pinctrl_can0_default: can0-default {
 
 /*
  * dts file for Xilinx ZynqMP zc1751-xm017-dc3
  *
- * (C) Copyright 2016 - 2019, Xilinx, Inc.
+ * (C) Copyright 2016 - 2021, Xilinx, Inc.
  *
  * Michal Simek <michal.simek@xilinx.com>
  */
        clock-frequency = <400000>;
 };
 
+/* MT29F64G08AECDBJ4-6 */
+&nand0 {
+       status = "okay";
+       arasan,has-mdma;
+       num-cs = <2>;
+};
+
 &rtc {
        status = "okay";
 };