coresight: tmc-etr: Handle memory errors

We have so far ignored the memory errors, assuming that we have perfect
hardware and driver. Let us handle the memory errors reported by the
TMC ETR in status and truncate the buffer.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
[Removed ASCII smiley face from changelog]
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20190829202842.580-6-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 3116d1f28e6601c0af85340b0908c55954a87a16..2246c1e6744a75cb84c1d00f5a83af9c3bce8e79 100644 (file)
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -928,6 +928,19 @@ static void tmc_sync_etr_buf(struct tmc_drvdata *drvdata)
        rrp = tmc_read_rrp(drvdata);
        rwp = tmc_read_rwp(drvdata);
        status = readl_relaxed(drvdata->base + TMC_STS);
+
+       /*
+        * If there were memory errors in the session, truncate the
+        * buffer.
+        */
+       if (WARN_ON_ONCE(status & TMC_STS_MEMERR)) {
+               dev_dbg(&drvdata->csdev->dev,
+                       "tmc memory error detected, truncating buffer\n");
+               etr_buf->len = 0;
+               etr_buf->full = 0;
+               return;
+       }
+
        etr_buf->full = status & TMC_STS_FULL;
 
        WARN_ON(!etr_buf->ops || !etr_buf->ops->sync);

diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
index 1ed50411cc3c34540fd1f7ebd3759241d55741a4..95d2e274797056b95c8291727b8d067a42293c35 100644 (file)
--- a/drivers/hwtracing/coresight/coresight-tmc.h
+++ b/drivers/hwtracing/coresight/coresight-tmc.h
@@ -47,6 +47,7 @@
 #define TMC_STS_TMCREADY_BIT   2
 #define TMC_STS_FULL           BIT(0)
 #define TMC_STS_TRIGGERED      BIT(1)
+#define TMC_STS_MEMERR         BIT(5)
 /*
  * TMC_AXICTL - 0x110
  *