arm64: tegra: Define missing IO ports
authorsheetal <sheetal@nvidia.com>
Wed, 7 Feb 2024 12:05:16 +0000 (17:35 +0530)
committerThierry Reding <treding@nvidia.com>
Fri, 23 Feb 2024 17:20:02 +0000 (18:20 +0100)
I2S3, I2S5, DMIC1, DMIC2, DMIC4, DSPK1 and DSPK2 IO ports are not
defined. Those are not defined earlier because it was inside platform
DT and defined only for supported IOs by the platform.
Now these are part of SoC DTSI, all IOs ports are defined
so that all the ports are available to be used by platforms.

Signed-off-by: sheetal <sheetal@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
arch/arm64/boot/dts/nvidia/tegra234.dtsi

index 9984f7441c9a858f779e83b5fade3aa04e08641c..06f334fd54269d937d71e784117190a9ea5d7e91 100644 (file)
                                        assigned-clock-rates = <1536000>;
                                        sound-name-prefix = "I2S3";
                                        status = "disabled";
+
+                                       ports {
+                                               #address-cells = <1>;
+                                               #size-cells = <0>;
+
+                                               port@0 {
+                                                       reg = <0>;
+
+                                                       i2s3_cif: endpoint {
+                                                               remote-endpoint = <&xbar_i2s3>;
+                                                       };
+                                               };
+
+                                               i2s3_port: port@1 {
+                                                       reg = <1>;
+
+                                                       i2s3_dap: endpoint {
+                                                               dai-format = "i2s";
+                                                               /* placeholder for external codec */
+                                                       };
+                                               };
+                                       };
                                };
 
                                tegra_i2s4: i2s@2901300 {
                                        assigned-clock-rates = <1536000>;
                                        sound-name-prefix = "I2S5";
                                        status = "disabled";
+
+                                       ports {
+                                               #address-cells = <1>;
+                                               #size-cells = <0>;
+
+                                               port@0 {
+                                                       reg = <0>;
+
+                                                       i2s5_cif: endpoint {
+                                                               remote-endpoint = <&xbar_i2s5>;
+                                                       };
+                                               };
+
+                                               i2s5_port: port@1 {
+                                                       reg = <1>;
+
+                                                       i2s5_dap: endpoint {
+                                                               dai-format = "i2s";
+                                                               /* placeholder for external codec */
+                                                       };
+                                               };
+                                       };
                                };
 
                                tegra_i2s6: i2s@2901500 {
                                        assigned-clock-rates = <3072000>;
                                        sound-name-prefix = "DMIC1";
                                        status = "disabled";
+
+                                       ports {
+                                               #address-cells = <1>;
+                                               #size-cells = <0>;
+
+                                               port@0 {
+                                                       reg = <0>;
+
+                                                       dmic1_cif: endpoint {
+                                                               remote-endpoint = <&xbar_dmic1>;
+                                                       };
+                                               };
+
+                                               dmic1_port: port@1 {
+                                                       reg = <1>;
+
+                                                       dmic1_dap: endpoint {
+                                                               /* placeholder for external codec */
+                                                       };
+                                               };
+                                       };
                                };
 
                                tegra_dmic2: dmic@2904100 {
                                        assigned-clock-rates = <3072000>;
                                        sound-name-prefix = "DMIC2";
                                        status = "disabled";
+
+                                       ports {
+                                               #address-cells = <1>;
+                                               #size-cells = <0>;
+
+                                               port@0 {
+                                                       reg = <0>;
+
+                                                       dmic2_cif: endpoint {
+                                                               remote-endpoint = <&xbar_dmic2>;
+                                                       };
+                                               };
+
+                                               dmic2_port: port@1 {
+                                                       reg = <1>;
+
+                                                       dmic2_dap: endpoint {
+                                                               /* placeholder for external codec */
+                                                       };
+                                               };
+                                       };
                                };
 
                                tegra_dmic3: dmic@2904200 {
                                        assigned-clock-rates = <3072000>;
                                        sound-name-prefix = "DMIC4";
                                        status = "disabled";
+
+                                       ports {
+                                               #address-cells = <1>;
+                                               #size-cells = <0>;
+
+                                               port@0 {
+                                                       reg = <0>;
+
+                                                       dmic4_cif: endpoint {
+                                                               remote-endpoint = <&xbar_dmic4>;
+                                                       };
+                                               };
+
+                                               dmic4_port: port@1 {
+                                                       reg = <1>;
+
+                                                       dmic4_dap: endpoint {
+                                                               /* placeholder for external codec */
+                                                       };
+                                               };
+                                       };
                                };
 
                                tegra_dspk1: dspk@2905000 {
                                        assigned-clock-rates = <12288000>;
                                        sound-name-prefix = "DSPK1";
                                        status = "disabled";
+
+                                       ports {
+                                               #address-cells = <1>;
+                                               #size-cells = <0>;
+
+                                               port@0 {
+                                                       reg = <0>;
+
+                                                       dspk1_cif: endpoint {
+                                                               remote-endpoint = <&xbar_dspk1>;
+                                                       };
+                                               };
+
+                                               dspk1_port: port@1 {
+                                                       reg = <1>;
+
+                                                       dspk1_dap: endpoint {
+                                                               /* placeholder for external codec */
+                                                       };
+                                               };
+                                       };
                                };
 
                                tegra_dspk2: dspk@2905100 {
                                        assigned-clock-rates = <12288000>;
                                        sound-name-prefix = "DSPK2";
                                        status = "disabled";
+
+                                       ports {
+                                               #address-cells = <1>;
+                                               #size-cells = <0>;
+
+                                               port@0 {
+                                                       reg = <0>;
+
+                                                       dspk2_cif: endpoint {
+                                                               remote-endpoint = <&xbar_dspk2>;
+                                                       };
+                                               };
+
+                                               dspk2_port: port@1 {
+                                                       reg = <1>;
+
+                                                       dspk2_dap: endpoint {
+                                                               /* placeholder for external codec */
+                                                       };
+                                               };
+                                       };
                                };
 
                                tegra_ope1: processing-engine@2908000 {
                                                };
                                        };
 
+                                       xbar_i2s3_port: port@16 {
+                                               reg = <0x16>;
+
+                                               xbar_i2s3: endpoint {
+                                                       remote-endpoint = <&i2s3_cif>;
+                                               };
+                                       };
+
                                        xbar_i2s4_port: port@17 {
                                                reg = <0x17>;
 
                                                };
                                        };
 
+                                       xbar_i2s5_port: port@18 {
+                                               reg = <0x18>;
+
+                                               xbar_i2s5: endpoint {
+                                                       remote-endpoint = <&i2s5_cif>;
+                                               };
+                                       };
+
                                        xbar_i2s6_port: port@19 {
                                                reg = <0x19>;
 
                                                };
                                        };
 
+                                       xbar_dmic1_port: port@1a {
+                                               reg = <0x1a>;
+
+                                               xbar_dmic1: endpoint {
+                                                       remote-endpoint = <&dmic1_cif>;
+                                               };
+                                       };
+
+                                       xbar_dmic2_port: port@1b {
+                                               reg = <0x1b>;
+
+                                               xbar_dmic2: endpoint {
+                                                       remote-endpoint = <&dmic2_cif>;
+                                               };
+                                       };
+
                                        xbar_dmic3_port: port@1c {
                                                reg = <0x1c>;
 
                                                };
                                        };
 
+                                       xbar_dmic4_port: port@1d {
+                                               reg = <0x1d>;
+
+                                               xbar_dmic4: endpoint {
+                                                       remote-endpoint = <&dmic4_cif>;
+                                               };
+                                       };
+
+                                       xbar_dspk1_port: port@1e {
+                                               reg = <0x1e>;
+
+                                               xbar_dspk1: endpoint {
+                                                       remote-endpoint = <&dspk1_cif>;
+                                               };
+                                       };
+
+                                       xbar_dspk2_port: port@1f {
+                                               reg = <0x1f>;
+
+                                               xbar_dspk2: endpoint {
+                                                       remote-endpoint = <&dspk2_cif>;
+                                               };
+                                       };
+
                                        xbar_sfc1_in_port: port@20 {
                                                reg = <0x20>;