ARM: dts: imx: add nvmem property for cpu0

Add nvmem related property for cpu0, then nvmem API could be used
to read cpu speed grading to avoid directly read OCOTP registers
mapped which could not handle defer probe.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index bba25d0697862892bae5396901d3bee5712407ef..77b65a402e197c3dfd8056363eb21466c491b5d0 100644 (file)
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -44,6 +44,8 @@
                        arm-supply = <&reg_arm>;
                        pu-supply = <&reg_pu>;
                        soc-supply = <&reg_soc>;
+                       nvmem-cells = <&cpu_speed_grade>;
+                       nvmem-cell-names = "speed_grade";
                };
 
                cpu@1 {

diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 907cf83066457e96631fbfb92a8b0ccdc2bf8b39..78a4d64929f38303d894a71138ca95dbdd972c79 100644 (file)
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -49,6 +49,8 @@
                        arm-supply = <&reg_arm>;
                        pu-supply = <&reg_pu>;
                        soc-supply = <&reg_soc>;
+                       nvmem-cells = <&cpu_speed_grade>;
+                       nvmem-cell-names = "speed_grade";
                };
 
                cpu1: cpu@1 {

diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 33efe7ec700648568fdc9285690e0a721fc18de9..47982889d7747a6e37f0e92db187ac7b77efa66a 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -1165,6 +1165,12 @@
                                compatible = "fsl,imx6q-ocotp", "syscon";
                                reg = <0x021bc000 0x4000>;
                                clocks = <&clks IMX6QDL_CLK_IIM>;
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+
+                               cpu_speed_grade: speed-grade@10 {
+                                       reg = <0x10 4>;
+                               };
                        };
 
                        tzasc@21d0000 { /* TZASC1 */

diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index c6141ed87e4dd8fb7b53af94a267f171a49de8d0..8230b45057a1896c12036d900ce2a4bfa8a1e77c 100644 (file)
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -74,6 +74,8 @@
                        arm-supply = <&reg_arm>;
                        pu-supply = <&reg_pu>;
                        soc-supply = <&reg_soc>;
+                       nvmem-cells = <&cpu_speed_grade>;
+                       nvmem-cell-names = "speed_grade";
                };
        };
 
@@ -953,6 +955,12 @@
                                compatible = "fsl,imx6sl-ocotp", "syscon";
                                reg = <0x021bc000 0x4000>;
                                clocks = <&clks IMX6SL_CLK_OCOTP>;
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+
+                               cpu_speed_grade: speed-grade@10 {
+                                       reg = <0x10 4>;
+                               };
                        };
 
                        audmux: audmux@21d8000 {

diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi
index e8e0fb334cfbdf1352692c86168ecce131f604b1..edd3abb9a9f19f8ff3fa531a9422ce22d47cda7c 100644 (file)
--- a/arch/arm/boot/dts/imx6sll.dtsi
+++ b/arch/arm/boot/dts/imx6sll.dtsi
@@ -72,6 +72,8 @@
                                 <&clks IMX6SLL_CLK_PLL1_SYS>;
                        clock-names = "arm", "pll2_pfd2_396m", "step",
                                      "pll1_sw", "pll1_sys";
+                       nvmem-cells = <&cpu_speed_grade>;
+                       nvmem-cell-names = "speed_grade";
                };
        };
 
@@ -791,6 +793,10 @@
                                reg = <0x021bc000 0x4000>;
                                clocks = <&clks IMX6SLL_CLK_OCOTP>;
 
+                               cpu_speed_grade: speed-grade@10 {
+                                       reg = <0x10 4>;
+                               };
+
                                tempmon_calib: calib@38 {
                                        reg = <0x38 4>;
                                };

diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index c48ef39db3fe3f94d65e324c56a16404f9a197bc..d6f831731460a49e7fabccc7c3157b23c7563d04 100644 (file)
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -87,6 +87,8 @@
                                      "pll1_sw", "pll1_sys";
                        arm-supply = <&reg_arm>;
                        soc-supply = <&reg_soc>;
+                       nvmem-cells = <&cpu_speed_grade>;
+                       nvmem-cell-names = "speed_grade";
                };
        };
 
@@ -1058,6 +1060,10 @@
                                reg = <0x021bc000 0x4000>;
                                clocks = <&clks IMX6SX_CLK_OCOTP>;
 
+                               cpu_speed_grade: speed-grade@10 {
+                                       reg = <0x10 4>;
+                               };
+
                                tempmon_calib: calib@38 {
                                        reg = <0x38 4>;
                                };