net/mlx5: Expose Management PCIe Index Register (MPIR)
authorTariq Toukan <tariqt@nvidia.com>
Mon, 7 Aug 2023 06:05:34 +0000 (09:05 +0300)
committerSaeed Mahameed <saeedm@nvidia.com>
Thu, 14 Dec 2023 02:03:30 +0000 (18:03 -0800)
MPIR register allows to query the PCIe indexes
and Socket-Direct related parameters.

Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Reviewed-by: Gal Pressman <gal@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h
drivers/net/ethernet/mellanox/mlx5/core/port.c
include/linux/mlx5/driver.h
include/linux/mlx5/mlx5_ifc.h

index 6b14e347d914203d63741e343ac3b977d49590d9..a79b7959361b5c324ebecd50e7038c1941a87f9b 100644 (file)
@@ -243,6 +243,7 @@ int mlx5_query_mcam_reg(struct mlx5_core_dev *dev, u32 *mcap, u8 feature_group,
                        u8 access_reg_group);
 int mlx5_query_qcam_reg(struct mlx5_core_dev *mdev, u32 *qcam,
                        u8 feature_group, u8 access_reg_group);
+int mlx5_query_mpir_reg(struct mlx5_core_dev *dev, u32 *mpir);
 
 void mlx5_lag_add_netdev(struct mlx5_core_dev *dev, struct net_device *netdev);
 void mlx5_lag_remove_netdev(struct mlx5_core_dev *dev, struct net_device *netdev);
index 7d8c732818f201673c8085904d78b426d5398c81..7fba1c46e2ac4a46ac1edbe04f04cce0182ae0cd 100644 (file)
@@ -1206,3 +1206,13 @@ int mlx5_port_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed)
        *speed = max_speed;
        return 0;
 }
+
+int mlx5_query_mpir_reg(struct mlx5_core_dev *dev, u32 *mpir)
+{
+       u32 in[MLX5_ST_SZ_DW(mpir_reg)] = {};
+       int sz = MLX5_ST_SZ_BYTES(mpir_reg);
+
+       MLX5_SET(mpir_reg, in, local_port, 1);
+
+       return mlx5_core_access_reg(dev, in, sz, mpir, sz, MLX5_REG_MPIR, 0, 0);
+}
index d2b8d4a74a30867a2275f4051132d0d7a96620c8..2f67cec1a898d74600f1c4f595df8a8a524ee4c2 100644 (file)
@@ -150,6 +150,7 @@ enum {
        MLX5_REG_MTPPSE          = 0x9054,
        MLX5_REG_MTUTC           = 0x9055,
        MLX5_REG_MPEGC           = 0x9056,
+       MLX5_REG_MPIR            = 0x9059,
        MLX5_REG_MCQS            = 0x9060,
        MLX5_REG_MCQI            = 0x9061,
        MLX5_REG_MCC             = 0x9062,
index 405d141b4a0852aa2ddc914c296c6dba87ca4584..828938368fb7f98c52a708088157c385d40e7ddf 100644 (file)
@@ -10108,6 +10108,20 @@ struct mlx5_ifc_mpegc_reg_bits {
        u8         reserved_at_60[0x100];
 };
 
+struct mlx5_ifc_mpir_reg_bits {
+       u8         sdm[0x1];
+       u8         reserved_at_1[0x1b];
+       u8         host_buses[0x4];
+
+       u8         reserved_at_20[0x20];
+
+       u8         local_port[0x8];
+       u8         reserved_at_28[0x15];
+       u8         sd_group[0x3];
+
+       u8         reserved_at_60[0x20];
+};
+
 enum {
        MLX5_MTUTC_FREQ_ADJ_UNITS_PPB          = 0x0,
        MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM   = 0x1,