arm64: dts: imx8mp: add HDMI power-domains

This adds the PGC and HDMI blk-ctrl nodes providing power control for
HDMI subsystem peripherals.

Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Tested-by: Marek Vasut <marex@denx.de>
Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index bfc5c81a5bd4eb44b2fb4cdf57ded83ccf8cb6e8..c9bcb6641de78bdb17bceab9967080995e07d71a 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -836,6 +836,23 @@
                                                         <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
                                        };
 
+                                       pgc_hdmimix: power-domain@14 {
+                                               #power-domain-cells = <0>;
+                                               reg = <IMX8MP_POWER_DOMAIN_HDMIMIX>;
+                                               clocks = <&clk IMX8MP_CLK_HDMI_ROOT>,
+                                                        <&clk IMX8MP_CLK_HDMI_APB>;
+                                               assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>,
+                                                                 <&clk IMX8MP_CLK_HDMI_APB>;
+                                               assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>,
+                                                                        <&clk IMX8MP_SYS_PLL1_133M>;
+                                               assigned-clock-rates = <500000000>, <133000000>;
+                                       };
+
+                                       pgc_hdmi_phy: power-domain@15 {
+                                               #power-domain-cells = <0>;
+                                               reg = <IMX8MP_POWER_DOMAIN_HDMI_PHY>;
+                                       };
+
                                        pgc_mipi_phy2: power-domain@16 {
                                                #power-domain-cells = <0>;
                                                reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>;
@@ -1889,6 +1906,27 @@
                                #power-domain-cells = <1>;
                                #clock-cells = <0>;
                        };
+
+                       hdmi_blk_ctrl: blk-ctrl@32fc0000 {
+                               compatible = "fsl,imx8mp-hdmi-blk-ctrl", "syscon";
+                               reg = <0x32fc0000 0x1000>;
+                               clocks = <&clk IMX8MP_CLK_HDMI_APB>,
+                                        <&clk IMX8MP_CLK_HDMI_ROOT>,
+                                        <&clk IMX8MP_CLK_HDMI_REF_266M>,
+                                        <&clk IMX8MP_CLK_HDMI_24M>,
+                                        <&clk IMX8MP_CLK_HDMI_FDCC_TST>;
+                               clock-names = "apb", "axi", "ref_266m", "ref_24m", "fdcc";
+                               power-domains = <&pgc_hdmimix>, <&pgc_hdmimix>,
+                                               <&pgc_hdmimix>, <&pgc_hdmimix>,
+                                               <&pgc_hdmimix>, <&pgc_hdmimix>,
+                                               <&pgc_hdmimix>, <&pgc_hdmi_phy>,
+                                               <&pgc_hdmimix>, <&pgc_hdmimix>;
+                               power-domain-names = "bus", "irqsteer", "lcdif",
+                                                    "pai", "pvi", "trng",
+                                                    "hdmi-tx", "hdmi-tx-phy",
+                                                    "hdcp", "hrv";
+                               #power-domain-cells = <1>;
+                       };
                };
 
                pcie: pcie@33800000 {