clk: tegra: Use fence_udelay() during PLLU init

This patch uses fence_udelay rather than udelay during PLLU
initialization to ensure writes to clock registers happens before
waiting for specified delay.

Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index d55f3da4287ab142bed9f19573f5492c137d9a02..134ba423103da98b69a2d4d845ed10de2a39929c 100644 (file)
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -2842,7 +2842,7 @@ static int tegra210_enable_pllu(void)
        reg = readl_relaxed(clk_base + pllu.params->ext_misc_reg[0]);
        reg &= ~BIT(pllu.params->iddq_bit_idx);
        writel_relaxed(reg, clk_base + pllu.params->ext_misc_reg[0]);
-       udelay(5);
+       fence_udelay(5, clk_base);
 
        reg = readl_relaxed(clk_base + PLLU_BASE);
        reg &= ~GENMASK(20, 0);
@@ -2850,7 +2850,7 @@ static int tegra210_enable_pllu(void)
        reg |= fentry->n << 8;
        reg |= fentry->p << 16;
        writel(reg, clk_base + PLLU_BASE);
-       udelay(1);
+       fence_udelay(1, clk_base);
        reg |= PLL_ENABLE;
        writel(reg, clk_base + PLLU_BASE);
 
@@ -2896,12 +2896,12 @@ static int tegra210_init_pllu(void)
                reg = readl_relaxed(clk_base + XUSB_PLL_CFG0);
                reg &= ~XUSB_PLL_CFG0_PLLU_LOCK_DLY_MASK;
                writel_relaxed(reg, clk_base + XUSB_PLL_CFG0);
-               udelay(1);
+               fence_udelay(1, clk_base);
 
                reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0);
                reg |= PLLU_HW_PWRDN_CFG0_SEQ_ENABLE;
                writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0);
-               udelay(1);
+               fence_udelay(1, clk_base);
 
                reg = readl_relaxed(clk_base + PLLU_BASE);
                reg &= ~PLLU_BASE_CLKENABLE_USB;