clk: qcom: gcc-ipq9574: Enable crypto clocks

Enable the clocks required for crypto operation.

Reviewed-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230526161129.1454-3-quic_anusha@quicinc.com

diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
index 7b0505f5c2553ef5ab346654de8df5f4386d7c52..6914f962c89367ffcc099681893851210ccc2673 100644 (file)
--- a/drivers/clk/qcom/gcc-ipq9574.c
+++ b/drivers/clk/qcom/gcc-ipq9574.c
@@ -728,6 +728,41 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
        },
 };
 
+static const struct freq_tbl ftbl_gcc_crypto_clk_src[] = {
+       F(160000000, P_GPLL0, 5, 0, 0),
+       { }
+};
+
+static struct clk_rcg2 gcc_crypto_clk_src = {
+       .cmd_rcgr = 0x16004,
+       .freq_tbl = ftbl_gcc_crypto_clk_src,
+       .hid_width = 5,
+       .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+       .clkr.hw.init = &(const struct clk_init_data) {
+               .name = "gcc_crypto_clk_src",
+               .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+               .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_branch gcc_crypto_clk = {
+       .halt_reg = 0x1600c,
+       .halt_check = BRANCH_HALT_VOTED,
+       .clkr = {
+               .enable_reg = 0x0b004,
+               .enable_mask = BIT(14),
+               .hw.init = &(const struct clk_init_data) {
+                       .name = "gcc_crypto_clk",
+                       .parent_hws = (const struct clk_hw *[]) {
+                               &gcc_crypto_clk_src.clkr.hw },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
 static struct clk_branch gcc_apss_ahb_clk = {
        .halt_reg = 0x24018,
        .halt_check = BRANCH_HALT_VOTED,
@@ -2071,6 +2106,38 @@ static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
        },
 };
 
+static struct clk_branch gcc_crypto_axi_clk = {
+       .halt_reg = 0x16010,
+       .clkr = {
+               .enable_reg = 0x16010,
+               .enable_mask = BIT(0),
+               .hw.init = &(const struct clk_init_data) {
+                       .name = "gcc_crypto_axi_clk",
+                       .parent_hws = (const struct clk_hw *[]) {
+                               &pcnoc_bfdcd_clk_src.clkr.hw },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_crypto_ahb_clk = {
+       .halt_reg = 0x16014,
+       .clkr = {
+               .enable_reg = 0x16014,
+               .enable_mask = BIT(0),
+               .hw.init = &(const struct clk_init_data) {
+                       .name = "gcc_crypto_ahb_clk",
+                       .parent_hws = (const struct clk_hw *[]) {
+                               &pcnoc_bfdcd_clk_src.clkr.hw },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
 static struct clk_branch gcc_nsscfg_clk = {
        .halt_reg = 0x1702c,
        .clkr = {
@@ -3880,6 +3947,10 @@ static struct clk_regmap *gcc_ipq9574_clks[] = {
        [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
        [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
        [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
+       [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
+       [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
+       [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
+       [GCC_CRYPTO_CLK_SRC] = &gcc_crypto_clk_src.clkr,
        [PCIE0_AXI_M_CLK_SRC] = &pcie0_axi_m_clk_src.clkr,
        [GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
        [PCIE1_AXI_M_CLK_SRC] = &pcie1_axi_m_clk_src.clkr,
@@ -4063,6 +4134,7 @@ static const struct qcom_reset_map gcc_ipq9574_resets[] = {
        [GCC_CMN_BLK_AHB_ARES] = { 0x3a010, 0 },
        [GCC_CMN_BLK_SYS_ARES] = { 0x3a010, 1 },
        [GCC_CMN_BLK_APU_ARES] = { 0x3a010, 2 },
+       [GCC_CRYPTO_BCR] = { 0x16000, 0 },
        [GCC_DCC_BCR] = { 0x35000, 0 },
        [GCC_DDRSS_BCR] = { 0x11000, 0 },
        [GCC_IMEM_BCR] = { 0x0e000, 0 },