drm/xe: Add performance tuning settings for MTL and Xe2

Add L3SQCREG5 as part of HW recommended settings. The recommended value
in Bspec is 00e0007f. For Xe2-LPG, bits 23:21 don't exist anymore, but
it's confirmed with HW engineers that setting them doesn't do anything.
They still exist on the media GT, Xe2-LPM, but they are already they are
already set as per HW default value. So for Xe2 platform, the only bits
that need to be set are 9:0 since HW's default is 0x1ff and the
recommended value is 0x7f.

Unlike most registers, which have the same relative offset on both
the primary and media GT, this register has a different base offset
on the media GT.

On MTL the register only exists for the primary (graphics) GT, so
there's no need to program it on the media gt. Also, it's part of the
RCS engine's context, so it needs to be added as a LRC workaround.

Bspec: 72161
Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20231024220739.224251-2-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 5ad75011aa70e2998dd1aa33bafaf7afdaba71ea..55ceadfc30b0b7aabce75f4bfb2f670dfcdfd6fc 100644 (file)
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -292,6 +292,8 @@
 
 #define XEHPC_L3CLOS_MASK(i)                   XE_REG_MCR(0xb194 + (i) * 8)
 
+#define XE2LPM_L3SQCREG5                       XE_REG_MCR(0xb658)
+
 #define XEHP_MERT_MOD_CTRL                     XE_REG_MCR(0xcf28)
 #define RENDER_MOD_CTRL                                XE_REG_MCR(0xcf2c)
 #define COMP_MOD_CTRL                          XE_REG_MCR(0xcf30)

diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
index d705198165220ff27ee31aae8923af29b421d006..53ccd338fd8c0c673253ed835da339a46184bf42 100644 (file)
--- a/drivers/gpu/drm/xe/xe_tuning.c
+++ b/drivers/gpu/drm/xe/xe_tuning.c
@@ -24,6 +24,20 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
          XE_RTP_RULES(PLATFORM(DG2)),
          XE_RTP_ACTIONS(SET(XEHP_SQCM, EN_32B_ACCESS))
        },
+
+       /* Xe2 */
+
+       { XE_RTP_NAME("Tuning: L3 cache"),
+         XE_RTP_RULES(GRAPHICS_VERSION(2004)),
+         XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
+                                  REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
+       },
+       { XE_RTP_NAME("Tuning: L3 cache - media"),
+         XE_RTP_RULES(MEDIA_VERSION(2000)),
+         XE_RTP_ACTIONS(FIELD_SET(XE2LPM_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
+                                  REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
+       },
+
        {}
 };
 
@@ -63,6 +77,15 @@ static const struct xe_rtp_entry_sr lrc_tunings[] = {
          XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
          XE_RTP_ACTIONS(SET(CHICKEN_RASTER_2, TBIMR_FAST_CLIP))
        },
+
+       /* Xe_LPG */
+
+       { XE_RTP_NAME("Tuning: L3 cache"),
+         XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271), ENGINE_CLASS(RENDER)),
+         XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
+                                  REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
+       },
+
        {}
 };