drm/bridge: ti-sn65dsi86: Code motion of refclk management functions

No functional changes--this just makes the diffstat of a future change
easier to understand.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20210423095743.v5.12.I047b8c7c6a3fc60eaca473da7a374f171fb021c2@changeid

diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
index 7f225009fd6cb65ec2a5941a9ae5a63785a5fbc8..5c2a91a4c293f9faf3022eaa5528adc445d4e68f 100644 (file)
--- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
+++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
@@ -192,6 +192,64 @@ static void ti_sn65dsi86_write_u16(struct ti_sn65dsi86 *pdata,
        regmap_write(pdata->regmap, reg + 1, val >> 8);
 }
 
+static u32 ti_sn_bridge_get_dsi_freq(struct ti_sn65dsi86 *pdata)
+{
+       u32 bit_rate_khz, clk_freq_khz;
+       struct drm_display_mode *mode =
+               &pdata->bridge.encoder->crtc->state->adjusted_mode;
+
+       bit_rate_khz = mode->clock *
+                       mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
+       clk_freq_khz = bit_rate_khz / (pdata->dsi->lanes * 2);
+
+       return clk_freq_khz;
+}
+
+/* clk frequencies supported by bridge in Hz in case derived from REFCLK pin */
+static const u32 ti_sn_bridge_refclk_lut[] = {
+       12000000,
+       19200000,
+       26000000,
+       27000000,
+       38400000,
+};
+
+/* clk frequencies supported by bridge in Hz in case derived from DACP/N pin */
+static const u32 ti_sn_bridge_dsiclk_lut[] = {
+       468000000,
+       384000000,
+       416000000,
+       486000000,
+       460800000,
+};
+
+static void ti_sn_bridge_set_refclk_freq(struct ti_sn65dsi86 *pdata)
+{
+       int i;
+       u32 refclk_rate;
+       const u32 *refclk_lut;
+       size_t refclk_lut_size;
+
+       if (pdata->refclk) {
+               refclk_rate = clk_get_rate(pdata->refclk);
+               refclk_lut = ti_sn_bridge_refclk_lut;
+               refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_refclk_lut);
+               clk_prepare_enable(pdata->refclk);
+       } else {
+               refclk_rate = ti_sn_bridge_get_dsi_freq(pdata) * 1000;
+               refclk_lut = ti_sn_bridge_dsiclk_lut;
+               refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_dsiclk_lut);
+       }
+
+       /* for i equals to refclk_lut_size means default frequency */
+       for (i = 0; i < refclk_lut_size; i++)
+               if (refclk_lut[i] == refclk_rate)
+                       break;
+
+       regmap_update_bits(pdata->regmap, SN_DPPLL_SRC_REG, REFCLK_FREQ_MASK,
+                          REFCLK_FREQ(i));
+}
+
 static int __maybe_unused ti_sn65dsi86_resume(struct device *dev)
 {
        struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev);
@@ -461,64 +519,6 @@ static void ti_sn_bridge_disable(struct drm_bridge *bridge)
        regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0);
 }
 
-static u32 ti_sn_bridge_get_dsi_freq(struct ti_sn65dsi86 *pdata)
-{
-       u32 bit_rate_khz, clk_freq_khz;
-       struct drm_display_mode *mode =
-               &pdata->bridge.encoder->crtc->state->adjusted_mode;
-
-       bit_rate_khz = mode->clock *
-                       mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
-       clk_freq_khz = bit_rate_khz / (pdata->dsi->lanes * 2);
-
-       return clk_freq_khz;
-}
-
-/* clk frequencies supported by bridge in Hz in case derived from REFCLK pin */
-static const u32 ti_sn_bridge_refclk_lut[] = {
-       12000000,
-       19200000,
-       26000000,
-       27000000,
-       38400000,
-};
-
-/* clk frequencies supported by bridge in Hz in case derived from DACP/N pin */
-static const u32 ti_sn_bridge_dsiclk_lut[] = {
-       468000000,
-       384000000,
-       416000000,
-       486000000,
-       460800000,
-};
-
-static void ti_sn_bridge_set_refclk_freq(struct ti_sn65dsi86 *pdata)
-{
-       int i;
-       u32 refclk_rate;
-       const u32 *refclk_lut;
-       size_t refclk_lut_size;
-
-       if (pdata->refclk) {
-               refclk_rate = clk_get_rate(pdata->refclk);
-               refclk_lut = ti_sn_bridge_refclk_lut;
-               refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_refclk_lut);
-               clk_prepare_enable(pdata->refclk);
-       } else {
-               refclk_rate = ti_sn_bridge_get_dsi_freq(pdata) * 1000;
-               refclk_lut = ti_sn_bridge_dsiclk_lut;
-               refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_dsiclk_lut);
-       }
-
-       /* for i equals to refclk_lut_size means default frequency */
-       for (i = 0; i < refclk_lut_size; i++)
-               if (refclk_lut[i] == refclk_rate)
-                       break;
-
-       regmap_update_bits(pdata->regmap, SN_DPPLL_SRC_REG, REFCLK_FREQ_MASK,
-                          REFCLK_FREQ(i));
-}
-
 static void ti_sn_bridge_set_dsi_rate(struct ti_sn65dsi86 *pdata)
 {
        unsigned int bit_rate_mhz, clk_freq_mhz;