{
        amdgpu_gfx_rlc_enter_safe_mode(adev);
 
-       if (is_support_sw_smu(adev) && !enable)
-               smu_set_gfx_cgpg(&adev->smu, enable);
-
        if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
                gfx_v9_0_enable_gfx_cg_power_gating(adev, true);
                if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
                        gfx_v9_0_enable_cp_power_gating(adev, false);
 
                /* update gfx cgpg state */
-               if (is_support_sw_smu(adev) && enable)
-                       smu_set_gfx_cgpg(&adev->smu, enable);
                gfx_v9_0_update_gfx_cg_power_gating(adev, enable);
 
                /* update mgcg state */
 
        if (adev->flags & AMD_IS_APU) {
                smu_powergate_sdma(&adev->smu, false);
                smu_powergate_vcn(&adev->smu, false);
+               smu_set_gfx_cgpg(&adev->smu, true);
        }
 
        if (!smu->pm_enabled)
        if (ret)
                goto failed;
 
+       if (smu->is_apu)
+               smu_set_gfx_cgpg(&adev->smu, true);
+
        mutex_unlock(&smu->mutex);
 
        pr_info("SMU is resumed successfully!\n");