drm/amd/display: Fix uninitialized variables in DC

This fixes 29 UNINIT issues reported by Coverity.

Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.c b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
index 86f9198e7501185048f582be4962c2597772ded1..2bcae0643e61dbeac9c2f216e337e732094a295d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
@@ -399,7 +399,7 @@ static enum bp_result transmitter_control_v1_6(
 static void init_transmitter_control(struct bios_parser *bp)
 {
        uint8_t frev;
-       uint8_t crev;
+       uint8_t crev = 0;
 
        if (BIOS_CMD_TABLE_REVISION(UNIPHYTransmitterControl,
                        frev, crev) == false)

diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
index cbae1be7b0093cfa76f4263055f90b4e9b358a64..cc000833d3001957f7e7c37714feacaf0b520133 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
@@ -225,7 +225,7 @@ static enum bp_result transmitter_control_fallback(
 static void init_transmitter_control(struct bios_parser *bp)
 {
        uint8_t frev;
-       uint8_t crev;
+       uint8_t crev = 0;
 
        BIOS_CMD_TABLE_REVISION(dig1transmittercontrol, frev, crev);
 

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
index 25d46c69464fc95cb13f2de03b321f4b82cc8a11..74da9ebda01611b97ee89ded8412fe10920ea9b9 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
@@ -2372,7 +2372,7 @@ validate_out:
 
 static struct _vcs_dpi_voltage_scaling_st construct_low_pstate_lvl(struct clk_limit_table *clk_table, unsigned int high_voltage_lvl)
 {
-       struct _vcs_dpi_voltage_scaling_st low_pstate_lvl;
+       struct _vcs_dpi_voltage_scaling_st low_pstate_lvl = {0};
        int i;
 
        low_pstate_lvl.state = 1;
@@ -2477,7 +2477,7 @@ void dcn201_populate_dml_writeback_from_context_fpu(struct dc *dc,
        int pipe_cnt, i, j;
        double max_calc_writeback_dispclk;
        double writeback_dispclk;
-       struct writeback_st dout_wb;
+       struct writeback_st dout_wb = {0};
 
        dc_assert_fp_enabled();
 

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
index ccb4ad78f6670657df8df469fd3a449ba1ea89b4..81f7b90849ce992f66b8e075a8130ea5e94f0049 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
@@ -260,7 +260,7 @@ void dcn30_fpu_populate_dml_writeback_from_context(
        int pipe_cnt, i, j;
        double max_calc_writeback_dispclk;
        double writeback_dispclk;
-       struct writeback_st dout_wb;
+       struct writeback_st dout_wb = {0};
 
        dc_assert_fp_enabled();
 

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index 5be976fa44f9ca6bce26e6048436ac2fae38f7e3..f6fe0a64beacf7b36a60322b7b3b7be22801ab16 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -723,7 +723,7 @@ static bool dcn32_enough_pipes_for_subvp(struct dc *dc, struct dc_state *context
  */
 static bool subvp_subvp_schedulable(struct dc *dc, struct dc_state *context)
 {
-       struct pipe_ctx *subvp_pipes[2];
+       struct pipe_ctx *subvp_pipes[2] = {0};
        struct dc_stream_state *phantom = NULL;
        uint32_t microschedule_lines = 0;
        uint32_t index = 0;

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
index 76399c66bc3baaf9dd7548f8eb8b4f0122e759d8..ba1310c8fd77401c8a562900ceec139359b4790c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
@@ -1973,8 +1973,8 @@ void dml32_CalculateVMRowAndSwath(
        unsigned int PTEBufferSizeInRequestsForChroma[DC__NUM_DPP__MAX];
        unsigned int PDEAndMetaPTEBytesFrameY;
        unsigned int PDEAndMetaPTEBytesFrameC;
-       unsigned int MetaRowByteY[DC__NUM_DPP__MAX];
-       unsigned int MetaRowByteC[DC__NUM_DPP__MAX];
+       unsigned int MetaRowByteY[DC__NUM_DPP__MAX] = {0};
+       unsigned int MetaRowByteC[DC__NUM_DPP__MAX] = {0};
        unsigned int PixelPTEBytesPerRowY[DC__NUM_DPP__MAX];
        unsigned int PixelPTEBytesPerRowC[DC__NUM_DPP__MAX];
        unsigned int PixelPTEBytesPerRowY_one_row_per_frame[DC__NUM_DPP__MAX];

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
index f43a31cd2c8ff84f9b250875a5d6c25136d2345a..a41812598ce84a716d695ed23fe7f0b19d83bf31 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
@@ -250,8 +250,8 @@ void dml2_init_soc_states(struct dml2_context *dml2, const struct dc *in_dc,
 {
        struct dml2_policy_build_synthetic_soc_states_scratch *s = &dml2->v20.scratch.create_scratch.build_synthetic_socbb_scratch;
        struct dml2_policy_build_synthetic_soc_states_params *p = &dml2->v20.scratch.build_synthetic_socbb_params;
-       unsigned int dcfclk_stas_mhz[NUM_DCFCLK_STAS];
-       unsigned int dcfclk_stas_mhz_new[NUM_DCFCLK_STAS_NEW];
+       unsigned int dcfclk_stas_mhz[NUM_DCFCLK_STAS] = {0};
+       unsigned int dcfclk_stas_mhz_new[NUM_DCFCLK_STAS_NEW] = {0};
        unsigned int dml_project = dml2->v20.dml_core_ctx.project;
 
        unsigned int i = 0;

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
index 961fc57e5183c5e0c734a5cedb66acdbb4cec60c..7d833fa6dd77c3e2f7faac177461122fa5906654 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
@@ -403,7 +403,7 @@ void dcn20_init_blank(
        struct output_pixel_processor *opp = NULL;
        struct output_pixel_processor *bottom_opp = NULL;
        uint32_t num_opps, opp_id_src0, opp_id_src1;
-       uint32_t otg_active_width, otg_active_height;
+       uint32_t otg_active_width = 0, otg_active_height = 0;
 
        /* program opp dpg blank color */
        color_space = COLOR_SPACE_SRGB;

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
index 093f4387553ce34ed55eb56c337e70b5c8e127bd..0d8a05cf8b1a1850c52fa3f54f755f09325c9dbd 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
@@ -82,7 +82,7 @@ static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
 
        if (enable) {
                struct dsc_config dsc_cfg;
-               struct dsc_optc_config dsc_optc_cfg;
+               struct dsc_optc_config dsc_optc_cfg = {0};
                enum optc_dsc_mode optc_dsc_mode;
 
                /* Enable DSC hw block */

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
index 9f1a86ddadb53f894c5426eb218853db3d328aa5..b8e884368dc6e5580bfb740d8872d9a7e578b907 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
@@ -989,7 +989,7 @@ static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
 
        if (enable) {
                struct dsc_config dsc_cfg;
-               struct dsc_optc_config dsc_optc_cfg;
+               struct dsc_optc_config dsc_optc_cfg = {0};
                enum optc_dsc_mode optc_dsc_mode;
 
                /* Enable DSC hw block */
@@ -1542,7 +1542,7 @@ void dcn32_init_blank(
        struct output_pixel_processor *opp = NULL;
        struct output_pixel_processor *bottom_opp = NULL;
        uint32_t num_opps, opp_id_src0, opp_id_src1;
-       uint32_t otg_active_width, otg_active_height;
+       uint32_t otg_active_width = 0, otg_active_height = 0;
        uint32_t i;
 
        /* program opp dpg blank color */

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
index b94a85380d73b72555cb4174c9a70b3424da67d3..d4989d15e2f1d1dbc41bb5d2f31d55c5bffba4ff 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
@@ -373,7 +373,7 @@ static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
 
        if (enable) {
                struct dsc_config dsc_cfg;
-               struct dsc_optc_config dsc_optc_cfg;
+               struct dsc_optc_config dsc_optc_cfg = {0};
                enum optc_dsc_mode optc_dsc_mode;
 
                /* Enable DSC hw block */

diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c b/drivers/gpu/drm/amd/display/dc/link/link_detection.c
index b8c4a04dd175789e92a4076ba5eb82a6aae573c4..0d523dc43d02af3aaf5f2f02cb1f65da4091576c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c
@@ -516,8 +516,8 @@ static void query_hdcp_capability(enum signal_type signal, struct dc_link *link)
 static void read_current_link_settings_on_detect(struct dc_link *link)
 {
        union lane_count_set lane_count_set = {0};
-       uint8_t link_bw_set;
-       uint8_t link_rate_set;
+       uint8_t link_bw_set = 0;
+       uint8_t link_rate_set = 0;
        uint32_t read_dpcd_retry_cnt = 10;
        enum dc_status status = DC_ERROR_UNEXPECTED;
        int i;

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
index 9de5380757e064ca39991a8a206833c136e03843..1818970b8eaf7a3ec4aade857841fc6f7af4b33b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
@@ -1071,7 +1071,7 @@ enum dc_status dpcd_set_link_settings(
                 * MUX chip gets link rate set back before link training.
                 */
                if (link->connector_signal == SIGNAL_TYPE_EDP) {
-                       uint8_t supported_link_rates[16];
+                       uint8_t supported_link_rates[16] = {0};
 
                        core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
                                        supported_link_rates, sizeof(supported_link_rates));

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
index 25cd6236b054efac8d87b4433b580baf5693b785..8bc1bcaeaa47d9c85c1d2e3112bc4cc1d7434c1e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
@@ -1143,7 +1143,7 @@ static bool dcn303_resource_construct(
        int i;
        struct dc_context *ctx = dc->ctx;
        struct irq_service_init_data init_data;
-       struct ddc_service_init_data ddc_init_data;
+       struct ddc_service_init_data ddc_init_data = {0};
 
        ctx->dc_bios->regs = &bios_regs;