drm/msm/dpu: plug-in the cdm related bits to writeback setup

To setup and enable CDM block for the writeback pipeline, lets
add the pieces together to set the active bits and the flush
bits for the CDM block.

changes in v2:
	- passed the cdm idx to update_pending_flush_cdm()
	  (have retained the R-b as its a minor change)

Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/571831/
Link: https://lore.kernel.org/r/20231212205254.12422-13-quic_abhinavk@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
index 9c87020c71198d3fbc68140e972485bdd67a8362..4cd2d9e3131a4325c1259b002a04fba73211a754 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
@@ -214,6 +214,7 @@ static void dpu_encoder_phys_wb_setup_ctl(struct dpu_encoder_phys *phys_enc)
 {
        struct dpu_hw_wb *hw_wb;
        struct dpu_hw_ctl *ctl;
+       struct dpu_hw_cdm *hw_cdm;
 
        if (!phys_enc) {
                DPU_ERROR("invalid encoder\n");
@@ -222,6 +223,7 @@ static void dpu_encoder_phys_wb_setup_ctl(struct dpu_encoder_phys *phys_enc)
 
        hw_wb = phys_enc->hw_wb;
        ctl = phys_enc->hw_ctl;
+       hw_cdm = phys_enc->hw_cdm;
 
        if (test_bit(DPU_CTL_ACTIVE_CFG, &ctl->caps->features) &&
                (phys_enc->hw_ctl &&
@@ -238,6 +240,9 @@ static void dpu_encoder_phys_wb_setup_ctl(struct dpu_encoder_phys *phys_enc)
                if (mode_3d && hw_pp && hw_pp->merge_3d)
                        intf_cfg.merge_3d = hw_pp->merge_3d->idx;
 
+               if (hw_cdm)
+                       intf_cfg.cdm = hw_cdm->idx;
+
                if (phys_enc->hw_pp->merge_3d && phys_enc->hw_pp->merge_3d->ops.setup_3d_mode)
                        phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d,
                                        mode_3d);
@@ -411,6 +416,7 @@ static void _dpu_encoder_phys_wb_update_flush(struct dpu_encoder_phys *phys_enc)
        struct dpu_hw_wb *hw_wb;
        struct dpu_hw_ctl *hw_ctl;
        struct dpu_hw_pingpong *hw_pp;
+       struct dpu_hw_cdm *hw_cdm;
        u32 pending_flush = 0;
 
        if (!phys_enc)
@@ -419,6 +425,7 @@ static void _dpu_encoder_phys_wb_update_flush(struct dpu_encoder_phys *phys_enc)
        hw_wb = phys_enc->hw_wb;
        hw_pp = phys_enc->hw_pp;
        hw_ctl = phys_enc->hw_ctl;
+       hw_cdm = phys_enc->hw_cdm;
 
        DPU_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
 
@@ -434,6 +441,9 @@ static void _dpu_encoder_phys_wb_update_flush(struct dpu_encoder_phys *phys_enc)
                hw_ctl->ops.update_pending_flush_merge_3d(hw_ctl,
                                hw_pp->merge_3d->idx);
 
+       if (hw_cdm && hw_ctl->ops.update_pending_flush_cdm)
+               hw_ctl->ops.update_pending_flush_cdm(hw_ctl, hw_cdm->idx);
+
        if (hw_ctl->ops.get_pending_flush)
                pending_flush = hw_ctl->ops.get_pending_flush(hw_ctl);