{ IMX93_CLK_HSIO_32K_GATE,      "hsio_32k",     "osc_32k",              0x9dc0, },
        { IMX93_CLK_ENET1_GATE,         "enet1",        "wakeup_axi_root",      0x9e00, },
        { IMX93_CLK_ENET_QOS_GATE,      "enet_qos",     "wakeup_axi_root",      0x9e40, },
-       { IMX93_CLK_SYS_CNT_GATE,       "sys_cnt",      "osc_24m",              0x9e80, },
+       /* Critical because clk accessed during CPU idle */
+       { IMX93_CLK_SYS_CNT_GATE,       "sys_cnt",      "osc_24m",              0x9e80, CLK_IS_CRITICAL},
        { IMX93_CLK_TSTMR1_GATE,        "tstmr1",       "bus_aon_root",         0x9ec0, },
        { IMX93_CLK_TSTMR2_GATE,        "tstmr2",       "bus_wakeup_root",      0x9f00, },
        { IMX93_CLK_TMC_GATE,           "tmc",          "osc_24m",              0x9f40, },