drm/i915: Rename the DSM/GSM registers

0x108100 and 0x1080c0 have been around since snb. Rename the
defines appropriately.

v2: Rebase

Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Acked-by: Nirmoy Das <nirmoy.das@intel.com>
Tested-by: Paz Zcharya <pazz@chromium.org>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240202224340.30647-7-ville.syrjala@linux.intel.com

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index 9ddcae9b399728e3f0755a57098669e1fc09bbb9..ad6dd7f3259bccb7de55c5622afd2a857ba6c2a8 100644 (file)
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -935,7 +935,7 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
                GEM_BUG_ON((dsm_base + dsm_size) > lmem_size);
        } else {
                /* Use DSM base address instead for stolen memory */
-               dsm_base = intel_uncore_read64(uncore, GEN12_DSMBASE) & GEN12_BDSM_MASK;
+               dsm_base = intel_uncore_read64(uncore, GEN6_DSMBASE) & GEN11_BDSM_MASK;
                if (WARN_ON(lmem_size < dsm_base))
                        return ERR_PTR(-ENODEV);
                dsm_size = ALIGN_DOWN(lmem_size - dsm_base, SZ_1M);
@@ -943,7 +943,7 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
 
        if (i915_direct_stolen_access(i915)) {
                drm_dbg(&i915->drm, "Using direct DSM access\n");
-               io_start = intel_uncore_read64(uncore, GEN12_DSMBASE) & GEN12_BDSM_MASK;
+               io_start = intel_uncore_read64(uncore, GEN6_DSMBASE) & GEN11_BDSM_MASK;
                io_size = dsm_size;
        } else if (pci_resource_len(pdev, GEN12_LMEM_BAR) < lmem_size) {
                io_start = 0;

diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index bce5d80253401031e24302e2a4901641e079e2c5..ec1cbe229f0e42c7be96f83da2cee40cc41bc93f 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -1163,7 +1163,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
 
        if (i915_direct_stolen_access(i915)) {
                drm_dbg(&i915->drm, "Using direct GSM access\n");
-               phys_addr = intel_uncore_read64(uncore, GEN12_GSMBASE) & GEN12_BDSM_MASK;
+               phys_addr = intel_uncore_read64(uncore, GEN6_GSMBASE) & GEN11_BDSM_MASK;
        } else {
                phys_addr = pci_resource_start(pdev, GEN4_GTTMMADR_BAR) + gen6_gttadr_offset(i915);
        }

diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index af357089da6eb29d60753f74ca70e8a1ec349675..51bb27e10a4f87190dbcaea020b10cbe1dea0fad 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -240,7 +240,7 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt)
                lmem_size -= tile_stolen;
        } else {
                /* Stolen starts from GSMBASE without CCS */
-               lmem_size = intel_uncore_read64(&i915->uncore, GEN12_GSMBASE);
+               lmem_size = intel_uncore_read64(&i915->uncore, GEN6_GSMBASE);
        }
 
        i915_resize_lmem_bar(i915, lmem_size);

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c1bf70d62ead00a997bcd4de2ecdae09b654d7af..e00557e1a57f0cc69ed71dd3dc0e29b8c06cebb1 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6325,9 +6325,10 @@ enum skl_power_gate {
 #define   GMS_MASK                     REG_GENMASK(15, 8)
 #define   GGMS_MASK                    REG_GENMASK(7, 6)
 
-#define GEN12_GSMBASE                  _MMIO(0x108100)
-#define GEN12_DSMBASE                  _MMIO(0x1080C0)
-#define   GEN12_BDSM_MASK              REG_GENMASK64(63, 20)
+#define GEN6_GSMBASE                   _MMIO(0x108100)
+#define GEN6_DSMBASE                   _MMIO(0x1080C0)
+#define   GEN6_BDSM_MASK               REG_GENMASK64(31, 20)
+#define   GEN11_BDSM_MASK              REG_GENMASK64(63, 20)
 
 #define XEHP_CLOCK_GATE_DIS            _MMIO(0x101014)
 #define   SGSI_SIDECLK_DIS             REG_BIT(17)