spi: cadence-quadspi: Add minimum operable clock rate warning to baudrate divisor...

This Cadence QSPI IP has a 4-bit clock divisor field
for baud rate division.  For example:

0b0000 = /2
0b0001 = /4
0b0010 = /6
...
0b1111 = /32

The maximum divisor is 32
(when div = CQSPI_REG_CONFIG_BAUD_MASK).

If we assume a reference clock of 500MHz and we set
our spi-max-frequency to something low, such as 10 MHz.
The calculated bit field for the divisor ends up being:

DIV_ROUND_UP(500000000/(2*10000000))-1 = 25

25 is 0b11001... which truncates to a divisor field of 0b1001 (or /20).

This is higher than our anticipated max-frequency of 10MHz
(500MHz/20 = 25 MHz).  Instead, let's make sure we're always using
the maximum divisor (/32) in this case and give the user a warning about
the rate adjustment.

Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
Link: https://lore.kernel.org/r/20221128164147.158441-1-nathan.morrison@timesys.com
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index 4219113cf36beb534dc1bfee0813d309a24a0af5..676313e1bdad130fd10349c332bd20e4d3f34f1a 100644 (file)
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -1119,6 +1119,14 @@ static void cqspi_config_baudrate_div(struct cqspi_st *cqspi)
        /* Recalculate the baudrate divisor based on QSPI specification. */
        div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1;
 
+       /* Maximum baud divisor */
+       if (div > CQSPI_REG_CONFIG_BAUD_MASK) {
+               div = CQSPI_REG_CONFIG_BAUD_MASK;
+               dev_warn(&cqspi->pdev->dev,
+                       "Unable to adjust clock <= %d hz. Reduced to %d hz\n",
+                       cqspi->sclk, ref_clk_hz/((div+1)*2));
+       }
+
        reg = readl(reg_base + CQSPI_REG_CONFIG);
        reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
        reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;