dmaengine: dw-axi-dmac: support parallel memory <--> peripheral transfers

Added support for multiple DMA_MEM_TO_DEV, DMA_DEV_TO_MEM transfers in
parallel. This is required for peripherals using DMA for transmit and
receive operations at the same time. APB slot number needs to be
programmed in channel hardware handshaking interface

Signed-off-by: Pandith N <pandith.n@intel.com>
Tested-by: Pan Kris <kris.pan@intel.com>
Link: https://lore.kernel.org/r/20210802055454.15192-3-pandith.n@intel.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index c3bb2b4820a343f1765edb0b2dae399196947f89..3edc647271b47d113773e2c2bbe0acfa701655c7 100644 (file)
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -363,12 +363,16 @@ static void axi_chan_block_xfer_start(struct axi_dma_chan *chan,
                        DWAXIDMAC_TT_FC_MEM_TO_PER_DST :
                        DWAXIDMAC_TT_FC_MEM_TO_PER_DMAC)
                        << CH_CFG_H_TT_FC_POS;
+               if (chan->chip->apb_regs)
+                       reg |= (chan->id << CH_CFG_H_DST_PER_POS);
                break;
        case DMA_DEV_TO_MEM:
                reg |= (chan->config.device_fc ?
                        DWAXIDMAC_TT_FC_PER_TO_MEM_SRC :
                        DWAXIDMAC_TT_FC_PER_TO_MEM_DMAC)
                        << CH_CFG_H_TT_FC_POS;
+               if (chan->chip->apb_regs)
+                       reg |= (chan->id << CH_CFG_H_SRC_PER_POS);
                break;
        default:
                break;

diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index 358f553cafe972801cbf29a4531278b7a3690c7a..380005afde160e244d9f4260a6a7d85c1d53f888 100644 (file)
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -258,6 +258,8 @@ enum {
 
 /* CH_CFG_H */
 #define CH_CFG_H_PRIORITY_POS          17
+#define CH_CFG_H_DST_PER_POS           12
+#define CH_CFG_H_SRC_PER_POS           7
 #define CH_CFG_H_HS_SEL_DST_POS                4
 #define CH_CFG_H_HS_SEL_SRC_POS                3
 enum {