arm64: dts: imx8m: align anatop with bindings

The CCM ANALOG module is used for generate PLLs, align the node
with DT bindings

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index afb90f59c83c5df18fa78e35fc409c621e6501b9..ea5feb04a0b7e2e921b9128cd8a79c8dbf95c083 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -573,9 +573,10 @@
                                };
                        };
 
-                       anatop: anatop@30360000 {
-                               compatible = "fsl,imx8mm-anatop", "syscon";
+                       anatop: clock-controller@30360000 {
+                               compatible = "fsl,imx8mm-anatop";
                                reg = <0x30360000 0x10000>;
+                               #clock-cells = <1>;
                        };
 
                        snvs: snvs@30370000 {

diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index cb2836bfbd95c7a3d7d354a6b63bea2e885f5925..fc86e73373135d0ecff80188bd21bc0347779ae2 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -576,10 +576,10 @@
                                };
                        };
 
-                       anatop: anatop@30360000 {
-                               compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop",
-                                            "syscon";
+                       anatop: clock-controller@30360000 {
+                               compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop";
                                reg = <0x30360000 0x10000>;
+                               #clock-cells = <1>;
                        };
 
                        snvs: snvs@30370000 {

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index bb916a0948a8f737d055f2925944915fb153109d..9f1b043c2f3fb27eab09dabf93ae25981a8335dd 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -441,10 +441,10 @@
                                };
                        };
 
-                       anatop: anatop@30360000 {
-                               compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop",
-                                            "syscon";
+                       anatop: clock-controller@30360000 {
+                               compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop";
                                reg = <0x30360000 0x10000>;
+                               #clock-cells = <1>;
                        };
 
                        snvs: snvs@30370000 {

diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 19eaa523564d3b7d3e8c7879b5ca8ea974f6349b..b14dbf2ffb9a73a1c132df2238d28109119ad17e 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -605,10 +605,11 @@
                                };
                        };
 
-                       anatop: syscon@30360000 {
-                               compatible = "fsl,imx8mq-anatop", "syscon";
+                       anatop: clock-controller@30360000 {
+                               compatible = "fsl,imx8mq-anatop";
                                reg = <0x30360000 0x10000>;
                                interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+                               #clock-cells = <1>;
                        };
 
                        snvs: snvs@30370000 {