}
}
}
-#endif
+
+#endif /* !CONFIG_USER_ONLY */
static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
int rw, int tlb_error)
}
#if !defined(CONFIG_USER_ONLY)
+
hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
MIPSCPU *cpu = MIPS_CPU(cs);
}
return phys_addr;
}
-#endif
+#endif /* !CONFIG_USER_ONLY */
#if !defined(CONFIG_USER_ONLY)
#if !defined(TARGET_MIPS64)
return true;
}
#endif
-#endif
+#endif /* !CONFIG_USER_ONLY */
bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
env->CP0_BadInstrP = cpu_ldl_code(env, env->active_tc.PC - 4);
}
}
-#endif
+
+#endif /* !CONFIG_USER_ONLY */
void mips_cpu_do_interrupt(CPUState *cs)
{
}
}
}
-#endif
+#endif /* !CONFIG_USER_ONLY */
void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
uint32_t exception,