arm64: dts: imx8mp: move PCIe controller clock config to SoC dtsi

The only difference in PCIe clock configuration between boards is how
the PCIe reference clock is generated. The refclock configuration is
fully contained in the PCIe PHY node, so the PCIe controller clocks
can be set up in the SoC dtsi, as there is no reason for any board to
use a different configuration.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index d4c7ca16abd057cc6bc6ff45de0404c9d51d5bae..c4ed505b87076523f301289377fbb21e12814828 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -400,13 +400,6 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pcie0>;
        reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;
-       clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
-                <&clk IMX8MP_CLK_PCIE_ROOT>,
-                <&clk IMX8MP_CLK_HSIO_AXI>;
-       clock-names = "pcie", "pcie_aux", "pcie_bus";
-       assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
-       assigned-clock-rates = <10000000>;
-       assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
        vpcie-supply = <&reg_pcie0>;
        status = "okay";
 };

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
index ceeca4966fc5c8a06694f38527691b2564f409db..007dd85fa086d12a7deb6f0989edcf2e79b2caa4 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
@@ -593,13 +593,6 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pcie0>;
        reset-gpio = <&gpio2 17 GPIO_ACTIVE_LOW>;
-       clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
-                <&clk IMX8MP_CLK_PCIE_ROOT>,
-                <&clk IMX8MP_CLK_HSIO_AXI>;
-       clock-names = "pcie", "pcie_aux", "pcie_bus";
-       assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
-       assigned-clock-rates = <10000000>;
-       assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
        status = "okay";
 };
 

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index dd2df83f6f27cecc3436f7091cacbbb4a2d3e533..a73509926e072f1f61fde90bd2837f007557d3ed 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -1202,6 +1202,13 @@
                        compatible = "fsl,imx8mp-pcie";
                        reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
                        reg-names = "dbi", "config";
+                       clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
+                                <&clk IMX8MP_CLK_PCIE_ROOT>,
+                                <&clk IMX8MP_CLK_HSIO_AXI>;
+                       clock-names = "pcie", "pcie_aux", "pcie_bus";
+                       assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
+                       assigned-clock-rates = <10000000>;
+                       assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
                        #address-cells = <3>;
                        #size-cells = <2>;
                        device_type = "pci";