dt-bindings: rng: st,rng: convert ST RNG to dtschema
authorKrzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Mon, 27 Dec 2021 18:32:50 +0000 (19:32 +0100)
committerRob Herring <robh@kernel.org>
Wed, 5 Jan 2022 13:31:41 +0000 (07:31 -0600)
Convert the ST RNG bindings to DT schema.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20211227183251.132525-7-krzysztof.kozlowski@canonical.com
Documentation/devicetree/bindings/rng/st,rng.txt [deleted file]
Documentation/devicetree/bindings/rng/st,rng.yaml [new file with mode: 0644]

diff --git a/Documentation/devicetree/bindings/rng/st,rng.txt b/Documentation/devicetree/bindings/rng/st,rng.txt
deleted file mode 100644 (file)
index 35734bc..0000000
+++ /dev/null
@@ -1,15 +0,0 @@
-STMicroelectronics HW Random Number Generator
-----------------------------------------------
-
-Required parameters:
-compatible     : Should be "st,rng"
-reg            : Base address and size of IP's register map.
-clocks         : Phandle to device's clock (See: ../clocks/clock-bindings.txt)
-
-Example:
-
-rng@fee80000 {
-       compatible      = "st,rng";
-       reg             = <0xfee80000 0x1000>;
-       clocks          = <&clk_sysin>;
-}
diff --git a/Documentation/devicetree/bindings/rng/st,rng.yaml b/Documentation/devicetree/bindings/rng/st,rng.yaml
new file mode 100644 (file)
index 0000000..ff1211e
--- /dev/null
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rng/st,rng.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectronics Hardware Random Number Generator
+
+maintainers:
+  - Patrice Chotard <patrice.chotard@foss.st.com>
+
+properties:
+  compatible:
+    const: st,rng
+
+  clocks:
+    maxItems: 1
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - clocks
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    rng@fee80000 {
+        compatible = "st,rng";
+        reg = <0xfee80000 0x1000>;
+        clocks = <&clk_sysin>;
+    };