clk: sunxi-ng: r40: Allow setting parent rate to display related clocks

Display related peripherals need precise clocks to operate correctly.

Allow DE2, TCONs and HDMI to set parent clock.

Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
index d52af1785644025602fb8ee71519c059f52f2e9a..0f388f6944d52e7a1d221778414ada120dd78994 100644 (file)
--- a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
@@ -656,7 +656,8 @@ static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace",     "dram",
 
 static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
 static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
-                                0x104, 0, 4, 24, 3, BIT(31), 0);
+                                0x104, 0, 4, 24, 3, BIT(31),
+                                CLK_SET_RATE_PARENT);
 static SUNXI_CCU_M_WITH_MUX_GATE(mp_clk, "mp", de_parents,
                                 0x108, 0, 4, 24, 3, BIT(31), 0);
 
@@ -668,9 +669,11 @@ static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd0_clk, "tcon-lcd0", tcon_parents,
 static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd1_clk, "tcon-lcd1", tcon_parents,
                               0x114, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
 static SUNXI_CCU_M_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0", tcon_parents,
-                                0x118, 0, 4, 24, 3, BIT(31), 0);
+                                0x118, 0, 4, 24, 3, BIT(31),
+                                CLK_SET_RATE_PARENT);
 static SUNXI_CCU_M_WITH_MUX_GATE(tcon_tv1_clk, "tcon-tv1", tcon_parents,
-                                0x11c, 0, 4, 24, 3, BIT(31), 0);
+                                0x11c, 0, 4, 24, 3, BIT(31),
+                                CLK_SET_RATE_PARENT);
 
 static const char * const deinterlace_parents[] = { "pll-periph0",
                                                    "pll-periph1" };
@@ -700,7 +703,8 @@ static SUNXI_CCU_GATE(avs_clk,              "avs",          "osc24M",
 
 static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" };
 static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
-                                0x150, 0, 4, 24, 2, BIT(31), 0);
+                                0x150, 0, 4, 24, 2, BIT(31),
+                                CLK_SET_RATE_PARENT);
 
 static SUNXI_CCU_GATE(hdmi_slow_clk,   "hdmi-slow",    "osc24M",
                      0x154, BIT(31), 0);