usb: dwc3: dwc3-octeon: Verify clock divider

Although valid USB clock divider will be calculated for all valid
Octeon core frequencies, make code formally correct limiting
divider not to be greater that 7 so it fits into H_CLKDIV_SEL
field.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reported-by: Linux Kernel Functional Testing <lkft@linaro.org>
Closes: https://qa-reports.linaro.org/lkft/linux-next-master/build/next-20230808/testrun/18882876/suite/build/test/gcc-8-cavium_octeon_defconfig/log
Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
Link: https://lore.kernel.org/r/ZNIM7tlBNdHFzXZG@lenoch
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/usb/dwc3/dwc3-octeon.c b/drivers/usb/dwc3/dwc3-octeon.c
index 6f47262a117a7563b0dd97aaf57d367a5dd8d85f..73bdcebf465c29e54c5b952469b59f1dc4371f63 100644 (file)
--- a/drivers/usb/dwc3/dwc3-octeon.c
+++ b/drivers/usb/dwc3/dwc3-octeon.c
@@ -251,11 +251,11 @@ static int dwc3_octeon_get_divider(void)
        while (div < ARRAY_SIZE(clk_div)) {
                uint64_t rate = octeon_get_io_clock_rate() / clk_div[div];
                if (rate <= 300000000 && rate >= 150000000)
-                       break;
+                       return div;
                div++;
        }
 
-       return div;
+       return -EINVAL;
 }
 
 static int dwc3_octeon_setup(struct dwc3_octeon *octeon,
@@ -289,6 +289,10 @@ static int dwc3_octeon_setup(struct dwc3_octeon *octeon,
 
        /* Step 4b: Select controller clock frequency. */
        div = dwc3_octeon_get_divider();
+       if (div < 0) {
+               dev_err(dev, "clock divider invalid\n");
+               return div;
+       }
        val = dwc3_octeon_readq(uctl_ctl_reg);
        val &= ~USBDRD_UCTL_CTL_H_CLKDIV_SEL;
        val |= FIELD_PREP(USBDRD_UCTL_CTL_H_CLKDIV_SEL, div);