drm/i915/gt: Drop a few unused register definitions

Let's drop a few register definitions that are unused anywhere in the
driver today.  Since the referenced offsets are part of what is now
considered a multicast register region, the current definitions would
not be correct for use on any future platform.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221014230239.1023689-4-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index ebc9a1d621319832c3861ed8be4ca7f6ebaecb60..be6f0066c2a801d2d72fcf11a3c394a54b3c73dd 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -451,13 +451,6 @@
 #define   GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC   REG_BIT(11)
 #define   GEN12_DISABLE_CPS_AWARE_COLOR_PIPE   REG_BIT(9)
 
-/* GEN9 chicken */
-#define SLICE_ECO_CHICKEN0                     _MMIO(0x7308)
-#define   PIXEL_MASK_CAMMING_DISABLE           (1 << 14)
-
-#define GEN9_SLICE_COMMON_ECO_CHICKEN0         _MMIO(0x7308)
-#define   DISABLE_PIXEL_MASK_CAMMING           (1 << 14)
-
 #define GEN9_SLICE_COMMON_ECO_CHICKEN1         _MMIO(0x731c)
 #define XEHP_SLICE_COMMON_ECO_CHICKEN1         _MMIO(0x731c)
 #define   MSC_MSAA_REODER_BUF_BYPASS_DISABLE   REG_BIT(14)
@@ -964,11 +957,6 @@
 #define GEN7_L3LOG(slice, i)                   _MMIO(0xb070 + (slice) * 0x200 + (i) * 4)
 #define   GEN7_L3LOG_SIZE                      0x80
 
-#define GEN10_SCRATCH_LNCF2                    _MMIO(0xb0a0)
-#define   PMFLUSHDONE_LNICRSDROP               (1 << 20)
-#define   PMFLUSH_GAPL3UNBLOCK                 (1 << 21)
-#define   PMFLUSHDONE_LNEBLK                   (1 << 22)
-
 #define XEHP_L3NODEARBCFG                      _MMIO(0xb0b4)
 #define   XEHP_LNESPARE                                REG_BIT(19)
 
@@ -983,9 +971,6 @@
 #define   L3_HIGH_PRIO_CREDITS(x)              (((x) >> 1) << 14)
 #define   L3_PRIO_CREDITS_MASK                 ((0x1f << 19) | (0x1f << 14))
 
-#define GEN10_L3_CHICKEN_MODE_REGISTER         _MMIO(0xb114)
-#define   GEN11_I2M_WRITE_DISABLE              (1 << 28)
-
 #define GEN8_L3SQCREG4                         _MMIO(0xb118)
 #define   GEN11_LQSC_CLEAN_EVICT_DISABLE       (1 << 6)
 #define   GEN8_LQSC_RO_PERF_DIS                        (1 << 27)
@@ -1188,8 +1173,6 @@
 #define SARB_CHICKEN1                          _MMIO(0xe90c)
 #define   COMP_CKN_IN                          REG_GENMASK(30, 29)
 
-#define GEN7_HALF_SLICE_CHICKEN1_GT2           _MMIO(0xf100)
-
 #define GEN7_ROW_CHICKEN2_GT2                  _MMIO(0xf4f4)
 #define   DOP_CLOCK_GATING_DISABLE             (1 << 0)
 #define   PUSH_CONSTANT_DEREF_DISABLE          (1 << 8)