DPU_ENCODER_FRAME_EVENT_ERROR);
 }
 
+static int dpu_encoder_helper_wait_event_timeout(int32_t drm_id,
+               int32_t hw_id, struct dpu_encoder_wait_info *info);
+
 int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc,
                enum dpu_intr_idx intr_idx,
                struct dpu_encoder_wait_info *wait_info)
        }
 }
 
-void dpu_encoder_destroy(struct drm_encoder *drm_enc)
+static void dpu_encoder_destroy(struct drm_encoder *drm_enc)
 {
        struct dpu_encoder_virt *dpu_enc = NULL;
        int i = 0;
        }
 }
 
-int dpu_encoder_helper_wait_event_timeout(
+static int dpu_encoder_helper_wait_event_timeout(
                int32_t drm_id,
                int32_t hw_id,
                struct dpu_encoder_wait_info *info)
 
 int dpu_encoder_setup(struct drm_device *dev, struct drm_encoder *enc,
                struct msm_display_info *disp_info);
 
-/**
- * dpu_encoder_destroy - destroy previously initialized virtual encoder
- * @drm_enc:    Pointer to previously created drm encoder structure
- */
-void dpu_encoder_destroy(struct drm_encoder *drm_enc);
-
 /**
  * dpu_encoder_prepare_commit - prepare encoder at the very beginning of an
  *     atomic commit, before any registers are written
 
  */
 void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc);
 
-/**
- * dpu_encoder_helper_wait_event_timeout - wait for event with timeout
- *     taking into account that jiffies may jump between reads leading to
- *     incorrectly detected timeouts. Prevent failure in this scenario by
- *     making sure that elapsed time during wait is valid.
- * @drm_id: drm object id for logging
- * @hw_id: hw instance id for logging
- * @info: wait info structure
- */
-int dpu_encoder_helper_wait_event_timeout(
-               int32_t drm_id,
-               int32_t hw_id,
-               struct dpu_encoder_wait_info *info);
-
 /**
  * dpu_encoder_helper_hw_reset - issue ctl hw reset
  *     This helper function may be optionally specified by physical
 
        return ret;
 }
 
-void dpu_encoder_phys_cmd_irq_control(struct dpu_encoder_phys *phys_enc,
+static void dpu_encoder_phys_cmd_irq_control(struct dpu_encoder_phys *phys_enc,
                bool enable)
 {
        struct dpu_encoder_phys_cmd *cmd_enc;
 
        return 0;
 }
 
-int dpu_format_get_plane_sizes(
+static int dpu_format_get_plane_sizes(
                const struct dpu_format *fmt,
                const uint32_t w,
                const uint32_t h,
 
                uint32_t pixel_formats_max);
 
 /**
- * dpu_format_get_plane_sizes - calculate size and layout of given buffer format
- * @fmt:             pointer to dpu_format
- * @w:               width of the buffer
- * @h:               height of the buffer
- * @layout:          layout of the buffer
- * @pitches:         array of size [DPU_MAX_PLANES] to populate
- *                  pitch for each plane
- *
- * Return: size of the buffer
- */
-int dpu_format_get_plane_sizes(
-               const struct dpu_format *fmt,
-               const uint32_t w,
-               const uint32_t h,
-               struct dpu_hw_fmt_layout *layout,
-               const uint32_t *pitches);
-
  * dpu_format_check_modified_format - validate format and buffers for
  *                   dpu non-standard, i.e. modified format
  * @kms:             kms driver
 
  * sdm845_cfg_init(): populate sdm845 dpu sub-blocks reg offsets
  * and instance counts.
  */
-void sdm845_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
+static void sdm845_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
 {
        *dpu_cfg = (struct dpu_mdss_cfg){
                .caps = &sdm845_dpu_caps,
 
        return 0;
 }
 
-int dpu_hw_cdm_enable(struct dpu_hw_cdm *ctx,
+static int dpu_hw_cdm_enable(struct dpu_hw_cdm *ctx,
                struct dpu_hw_cdm_cfg *cdm)
 {
        struct dpu_hw_blk_reg_map *c = &ctx->hw;
        return 0;
 }
 
-void dpu_hw_cdm_disable(struct dpu_hw_cdm *ctx)
+static void dpu_hw_cdm_disable(struct dpu_hw_cdm *ctx)
 {
        struct cdm_output_cfg cdm_cfg = { 0 };
 
 
        status->sspp[SSPP_CURSOR1] = (value >> 26) & 0x1;
 }
 
-void dpu_hw_reset_ubwc(struct dpu_hw_mdp *mdp, struct dpu_mdss_cfg *m)
+static void dpu_hw_reset_ubwc(struct dpu_hw_mdp *mdp, struct dpu_mdss_cfg *m)
 {
        struct dpu_hw_blk_reg_map c;
 
 
        return 0;
 }
 
-void _dpu_kms_set_encoder_mode(struct msm_kms *kms,
+static void _dpu_kms_set_encoder_mode(struct msm_kms *kms,
                                 struct drm_encoder *encoder,
                                 bool cmd_mode)
 {
 
        return 0;
 }
 
-int _dpu_mdss_irq_domain_fini(struct dpu_mdss *dpu_mdss)
+static int _dpu_mdss_irq_domain_fini(struct dpu_mdss *dpu_mdss)
 {
        if (dpu_mdss->irq_controller.domain) {
                irq_domain_remove(dpu_mdss->irq_controller.domain);