--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_UFS_V3_H_
+#define QCOM_PHY_QMP_PCS_UFS_V3_H_
+
+#define QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL           0x02c
+#define QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL           0x034
+#define QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL             0x134
+#define QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME            0x138
+#define QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1                        0x13c
+#define QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2                        0x140
+#define QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1              0x1bc
+#define QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1               0x1c4
+
+#endif
 
 #define QPHY_V3_PCS_TXMGN_V3                           0x018
 #define QPHY_V3_PCS_TXMGN_V4                           0x01c
 #define QPHY_V3_PCS_TXMGN_LS                           0x020
-#define QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL               0x02c
-#define QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL               0x034
 #define QPHY_V3_PCS_TXDEEMPH_M6DB_V0                   0x024
 #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0                 0x028
 #define QPHY_V3_PCS_TXDEEMPH_M6DB_V1                   0x02c
 #define QPHY_V3_PCS_FLL_CNT_VAL_L                      0x0cc
 #define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL                  0x0d0
 #define QPHY_V3_PCS_FLL_MAN_CODE                       0x0d4
-#define QPHY_V3_PCS_RX_SYM_RESYNC_CTRL                 0x134
-#define QPHY_V3_PCS_RX_MIN_HIBERN8_TIME                        0x138
-#define QPHY_V3_PCS_RX_SIGDET_CTRL1                    0x13c
-#define QPHY_V3_PCS_RX_SIGDET_CTRL2                    0x140
 #define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB      0x1a8
 #define QPHY_V3_PCS_OSC_DTCT_ACTIONS                   0x1ac
 #define QPHY_V3_PCS_SIGDET_CNTRL                       0x1b0
-#define QPHY_V3_PCS_TX_MID_TERM_CTRL1                  0x1bc
-#define QPHY_V3_PCS_MULTI_LANE_CTRL1                   0x1c4
 #define QPHY_V3_PCS_RX_SIGDET_LVL                      0x1d8
 #define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB    0x1dc
 #define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB    0x1e0
 
 };
 
 static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
-       QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
-       QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
-       QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
-       QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
-       QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
-       QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
-       QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
-       QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2, 0x6e),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1, 0x0f),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME, 0x9a),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
 };
 
 static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
 
        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
-       QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
+       QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
 
 
 #include "phy-qcom-qmp-pcs-v3.h"
 #include "phy-qcom-qmp-pcs-misc-v3.h"
+#include "phy-qcom-qmp-pcs-ufs-v3.h"
 
 #include "phy-qcom-qmp-pcs-v4.h"
 #include "phy-qcom-qmp-pcs-pcie-v4.h"