drm/i915/dsi: let HW maintain CLK_POST
authorWilliam Tseng <william.tseng@intel.com>
Thu, 14 Sep 2023 09:51:37 +0000 (17:51 +0800)
committerJani Nikula <jani.nikula@intel.com>
Wed, 20 Sep 2023 17:16:09 +0000 (20:16 +0300)
This change is to adjust TCLK-POST timing so DSI signaling can
meet CTS specification.

For clock lane, the TCLK-POST timing may be changed from
133.44 ns to 178.72 ns, which is greater than (60 ns+52*UI)
and is conformed to the CTS standard.

The computed UI is around 1.47 ns.

v2: remove the change of HS-TRAIL.

Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Cc: Lee Shawn C <shawn.c.lee@intel.com>
Signed-off-by: William Tseng <william.tseng@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230914095137.4132029-1-william.tseng@intel.com
drivers/gpu/drm/i915/display/icl_dsi.c

index ad6488e9c2b2b8b97bb45c9d70913214ed412551..c4585e445198d3a3f51c6398b3b14dbe8ba9adea 100644 (file)
@@ -1822,7 +1822,7 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
        u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
        u32 ths_prepare_ns, tclk_trail_ns;
        u32 hs_zero_cnt;
-       u32 tclk_pre_cnt, tclk_post_cnt;
+       u32 tclk_pre_cnt;
 
        tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
 
@@ -1869,15 +1869,6 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
                tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX;
        }
 
-       /* tclk post count in escape clocks */
-       tclk_post_cnt = DIV_ROUND_UP(mipi_config->tclk_post, tlpx_ns);
-       if (tclk_post_cnt > ICL_TCLK_POST_CNT_MAX) {
-               drm_dbg_kms(&dev_priv->drm,
-                           "tclk_post_cnt out of range (%d)\n",
-                           tclk_post_cnt);
-               tclk_post_cnt = ICL_TCLK_POST_CNT_MAX;
-       }
-
        /* hs zero cnt in escape clocks */
        hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero -
                                   ths_prepare_ns, tlpx_ns);
@@ -1903,8 +1894,6 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
                               CLK_ZERO(clk_zero_cnt) |
                               CLK_PRE_OVERRIDE |
                               CLK_PRE(tclk_pre_cnt) |
-                              CLK_POST_OVERRIDE |
-                              CLK_POST(tclk_post_cnt) |
                               CLK_TRAIL_OVERRIDE |
                               CLK_TRAIL(trail_cnt));