arm64: zynqmp: Switch to ethernet-phy-id in kv260
authorMichal Simek <michal.simek@amd.com>
Tue, 2 May 2023 13:35:45 +0000 (15:35 +0200)
committerMichal Simek <michal.simek@amd.com>
Tue, 16 May 2023 12:50:15 +0000 (14:50 +0200)
Use ethernet-phy-id compatible string to properly describe phy reset on
kv260 boards. Previous description wasn't correct because reset was done
for mdio bus to operate and it was in this case used for different purpose
which was eth phy reset. With ethernet-phy-id phy reset happens only for
the phy via phy framework.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/4b139e942c2a808eecbb30226b6ea5303348390a.1683034376.git.michal.simek@amd.com
arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso

index 22fe9c4e4d4373c3d96afe1f229acb84efc03a80..85bf276fb52dcc127d1704bb1ea43ad1a1763c60 100644 (file)
        mdio: mdio {
                #address-cells = <1>;
                #size-cells = <0>;
-               reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
-               reset-delay-us = <2>;
 
                phy0: ethernet-phy@1 {
                        #phy-cells = <1>;
                        reg = <1>;
+                       compatible = "ethernet-phy-id2000.a231";
                        ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
                        ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
                        ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
                        ti,dp83867-rxctrl-strap-quirk;
+                       reset-assert-us = <100>;
+                       reset-deassert-us = <280>;
+                       reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
                };
        };
 };
index ca3429f9961ac4f1470e79b4b390dbd1c612ab12..bf8f2a94be251040eecff0d9c8d623aa2c6c6673 100644 (file)
        mdio: mdio {
                #address-cells = <1>;
                #size-cells = <0>;
-               reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
-               reset-delay-us = <2>;
 
                phy0: ethernet-phy@1 {
                        #phy-cells = <1>;
                        reg = <1>;
+                       compatible = "ethernet-phy-id2000.a231";
                        ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
                        ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
                        ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
                        ti,dp83867-rxctrl-strap-quirk;
+                       reset-assert-us = <100>;
+                       reset-deassert-us = <280>;
+                       reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
                };
        };
 };