arm64: dts: rockchip: rk3568-evb1-v10: add ethernet support

Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
Link: https://lore.kernel.org/r/20210729093913.8917-3-michael.riesch@wolfvision.net
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
index 69786557093dae74499101fca73a75e510eb74e8..65e536c78d2e1f67a27f3444dbcd215cf315a0bb 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
@@ -13,6 +13,11 @@
        model = "Rockchip RK3568 EVB1 DDR4 V10 Board";
        compatible = "rockchip,rk3568-evb1-v10", "rockchip,rk3568";
 
+       aliases {
+               ethernet0 = &gmac0;
+               ethernet1 = &gmac1;
+       };
+
        chosen: chosen {
                stdout-path = "serial2:1500000n8";
        };
@@ -67,6 +72,58 @@
        };
 };
 
+&gmac0 {
+       assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+       assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
+       assigned-clock-rates = <0>, <125000000>;
+       clock_in_out = "output";
+       phy-handle = <&rgmii_phy0>;
+       phy-mode = "rgmii-id";
+       pinctrl-names = "default";
+       pinctrl-0 = <&gmac0_miim
+                    &gmac0_tx_bus2
+                    &gmac0_rx_bus2
+                    &gmac0_rgmii_clk
+                    &gmac0_rgmii_bus>;
+       status = "okay";
+};
+
+&gmac1 {
+       assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+       assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
+       assigned-clock-rates = <0>, <125000000>;
+       clock_in_out = "output";
+       phy-handle = <&rgmii_phy1>;
+       phy-mode = "rgmii-id";
+       pinctrl-names = "default";
+       pinctrl-0 = <&gmac1m1_miim
+                    &gmac1m1_tx_bus2
+                    &gmac1m1_rx_bus2
+                    &gmac1m1_rgmii_clk
+                    &gmac1m1_rgmii_bus>;
+       status = "okay";
+};
+
+&mdio0 {
+       rgmii_phy0: ethernet-phy@0 {
+               compatible = "ethernet-phy-ieee802.3-c22";
+               reg = <0x0>;
+               reset-assert-us = <20000>;
+               reset-deassert-us = <100000>;
+               reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
+       };
+};
+
+&mdio1 {
+       rgmii_phy1: ethernet-phy@0 {
+               compatible = "ethernet-phy-ieee802.3-c22";
+               reg = <0x0>;
+               reset-assert-us = <20000>;
+               reset-deassert-us = <100000>;
+               reset-gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
+       };
+};
+
 &sdhci {
        bus-width = <8>;
        max-frequency = <200000000>;